UT62L1024PC-55LE(Rev1_1) 데이터 시트보기 (PDF) - Utron Technology Inc

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UT62L1024PC-55LE
(Rev.:Rev1_1)

128K X 8 BIT LOW POWER CMOS SRAM

Utron Technology Inc 



UTRON

Rev. 1.1

UT62L1024(E)

128K X 8 BIT LOW POWER CMOS SRAM

DATA RETENTION CHARACTERISTICS (TA = -20℃~80℃)

PARAMETER

Vcc for Data Retention

Data Retention Current

SYMBOL TEST CONDITION

VDR

CE1 ≧ VCC-0.2V or CE2 ≤ 0.2V

IDR

Vcc=3V

-L

CE1 ≧ VCC-0.2V or

- LL

CE2 ≤ 0.2V

Chip Disable to Data

Retention Time

tCDR See Data Retention

Waveforms (below)

Recovery Time

tR

tRC* = Read Cycle Time

*Those parameters are for reference only under 50℃

MIN.

2.0

-

TYP.

-

1

-

0.3

0

-

MAX.

-

60

10*

30

10*

-

UNIT

V

µA

µA

ns

tRC*

-

-

ns

DATA RETENTION WAVEFORM

VCC

CE1

VSS

CE2

2.7V

tCDR

VIH

VIL

Date Retention Mode

VDR ≧ 2.0V

CE1 ≧ VCC -0.2V

CE2 ≤ 0.2V

2.7V

tR

VIH

VIL

UTRON TECHNOLOGY INC.

1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.

TEL: 886-3-5777882 FAX: 886-3-5777919

6

P80053

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