SJA1000T 데이터 시트보기 (PDF) - NXP Semiconductors.
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SJA1000T Datasheet PDF : 68 Pages
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Philips Semiconductors
Stand-alone CAN controller
Product specification
SJA1000
Table 1 BasicCAN address allocation; note 1
CAN
ADDRESS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
SEGMENT
OPERATING MODE
READ
WRITE
control
control
control
(FFH)
command
status
−
interrupt
−
(FFH)
−
(FFH)
−
(FFH)
−
(FFH)
−
(FFH)
−
test
test; note 2
transmit
buffer
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 1
data byte 2
data byte 2
data byte 3
data byte 3
data byte 4
data byte 4
data byte 5
data byte 5
data byte 6
data byte 6
data byte 7
data byte 7
data byte 8
data byte 8
receive
buffer
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 1
data byte 2
data byte 2
data byte 3
data byte 3
data byte 4
data byte 4
data byte 5
data byte 5
data byte 6
data byte 6
data byte 7
data byte 7
data byte 8
data byte 8
(FFH)
clock divider
−
clock divider; note 3
RESET MODE
READ
control
(FFH)
status
interrupt
acceptance code
acceptance mask
bus timing 0
bus timing 1
output control
test
(FFH)
(FFH)
WRITE
control
command
−
−
acceptance code
acceptance mask
bus timing 0
bus timing 1
output control
test; note 2
−
−
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
(FFH)
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
(FFH)
clock divider
−
−
−
−
−
−
−
−
identifier (10 to 3)
identifier (2 to 0),
RTR and DLC
data byte 1
data byte 2
data byte 3
data byte 4
data byte 5
data byte 6
data byte 7
data byte 8
−
clock divider
Notes
1. It should be noted that the registers are repeated within higher CAN address areas (the most significant bits of the
8-bit CPU address are not decoded: CAN address 32 continues with CAN address 0 and so on).
2. Test register is used for production testing only. Using this register during normal operation may result in undesired
behaviour of the device.
3. Some bits are writeable in reset mode only (CAN mode and CBP).
2000 Jan 04
9
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