SI5328 데이터 시트보기 (PDF) - Silicon Laboratories

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SI5328

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Table 2. DC Characteristics (Continued)

(VDD = 2.5 V ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Output Drive Current

(CMOS driving into

CKOVOL for output low

or CKOVOH for output

high. CKOUT+ and

CKOUT– shorted

externally)

CKOIO

2-Level LVCMOS Input Pins

ICMOS[1:0] =11

VDD = 2.5 V

ICMOS[1:0] =10

VDD = 2.5 V

ICMOS[1:0] =01

VDD = 2.5 V

ICMOS[1:0] =00

VDD = 2.5 V

ICMOS[1:0] = 11

VDD = 3.3 V

ICMOS[1:0] =10

VDD = 3.3 V

ICMOS[1:0] =01

VDD = 3.3 V

ICMOS[1:0] =00

VDD = 3.3 V

Min

Typ

—

20

—

15

—

10

—

5

—

32

—

24

—

16

—

8

Max

Unit

—

mA

—

mA

—

mA

—

mA

—

mA

—

mA

—

mA

—

mA

Input Voltage Low

VIL

VDD = 2.25 V

—

—

0.7

V

VDD = 2.97 V

—

—

0.8

V

Input Voltage High

VIH

VDD = 2.25 V

1.8

—

—

V

VDD = 3.63 V

2.5

—

—

V

Notes:

1. Current draw is independent of supply voltage

2. No under- or overshoot is allowed.

3. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 312.5 MHz.

4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family

Reference Manual for more details.

Rev. 1.0

7

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