SI5328C-C-GMR 데이터 시트보기 (PDF) - Silicon Laboratories

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SI5328C-C-GMR

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Table 3. AC Characteristics (Continued)

(VDD = 2.5 ±10% or 3.3 V ±10%, TA = –40 to 85 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Output Rise/Fall

(20–80%) @

CKOTRF LVPECL, LVDS or CML

—

230

350

ps

Output

312.5 MHz output

Output Duty Cycle

Uncertainty @

CKODC

100  Load

Line-to-Line

45

—

55

%

808 MHz

Measured at 50% Point

(Not for CMOS)

LVCMOS Input Pins

Minimum Reset Pulse

Width

Reset to Microproces-

sor Access Ready

Input Capacitance

LVCMOS Output Pins

tRSTMN

tREADY

Cin

1

µs

10

ms

—

—

3

pF

Rise/Fall Times

tRF

CLOAD = 20pf

—

See Figure 2

LOSn Trigger Window LOSTRIG From last CKINn to 

—

Internal detection of LOSn

N3 ≠ 1

Time to Clear LOL

tCLRLOL

LOS to LOL

—

after LOS Cleared

Fold = Fnew

Stable Xa/XB reference

Device Skew

25

—

ns

—

4.5 x N3 TCKIN

10

—

ms

Output Clock Skew

tSKEW

 of CKOUTn to  of

—

—

100

ps

CKOUT_m, CKOUTn

and CKOUT_m at same

frequency and signal

format

PHASEOFFSET = 0

CKOUT_ALWAYS_ON = 1

SQ_ICAL = 1

Phase Change due to

tTEMP Max phase changes from –

—

300

500

ps

Temperature Variation

40 to +85 °C, stable XAXB

reference

Notes:

1. Lock and settle times may change with different f3, loop BW, and VCO frequency values. Contact Silicon Labs for

further details.

2. See Section 9 of “AN775: Si5328 Synchronous Ethernet Compliance Test Report” for more details.

10

Rev. 1.0

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