MC-4R96CPE6C-653 데이터 시트보기 (PDF) - NEC => Renesas Technology

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MC-4R96CPE6C-653

Direct Rambus™ DRAM RIMM™ Module 96M-BYTE (48M-WORD x 16-BIT)

NEC => Renesas Technology 

MC-4R96CPE6C

AC Electrical Specifications

Symbol

Parameter and Conditions

MIN. TYP. MAX. Unit

•Z

Module Impedance

25.2

28

30.8 Ω

TPD

Average clock delay from finger to finger of all RSL clock nets

-845

1.40 ns

(CTM, CTMN,CFM, and CFMN)

-745

1.40

∆TPD

-653

Propagation delay variation of RSL signals with respect to TPD Note1,2

−21

1.40

+21 ps

∆TPD-CMOS Propagation delay variation of SCK and CMD signals with respect to

an average clock delay Note1

Vα/VIN

Attenuation Limit

−100

-845

+100 ps

14

%

-745

14

-653

9

VXF/VIN Forward crosstalk coefficient

-845

3

%

(300ps input rise time 20% - 80%)

-745

3

-653

3

VXB/VIN Backward crosstalk coefficient

-845

1.8

%

(300ps input rise time 20% - 80%)

-745

1.8

-653

1.8

RDC

DC Resistance Limit

-845

0.7

Ω

-745

0.7

-653

0.7

Notes 1. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,

CTMN, CFM, and CFMN).

2. If the RIMM module meets the following specification, then it is compliant to the specification.

If the RIMM module does not meet these specifications, then the specification can be adjusted by the

“Adjusted ∆TPD Specification” table.

Adjusted ∆TPD Specification

Symbol

Parameter and conditions

Adjusted MIN./MAX.

Absolute

Unit

MIN. MAX.

∆TPD Propagation delay variation of RSL signals with respect to TPD +/− [17+(18*N*∆Z0)] Note −30

+30

ps

Note N = Number of RDRAM devices installed on the RIMM module.

∆Z0 = delta Z0% = (MAX. Z0 − MIN. Z0) / (MIN. Z0)

(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers

on the module.)

Preliminary Data Sheet M14806EJ2V0DS00

9

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