AKD4363 데이터 시트보기 (PDF) - Asahi Kasei Microdevices

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AKD4363

96kHz 24Bit ∆Σ DAC with PLL

Asahi Kasei Microdevices 

ASAHI KASEI

[AK4363]

n Power-down

The DAC is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same time.

The internal register values are initialized by PDN “L”. This reset should always be done after power-up. Because some

click noise occurs at the edge of PDN, the analog output should be muted externally if the click noise influences system

application.

PDN

Internal

State

D/A In

(Digital)

D/A Out

(Analog)

Clock In

MCKI, LRCK, BICK

Normal Operation

Power-down

“0” data

GD (1)

(3) (2)

(4)

Don’t care

Normal Operation

GD (1)

(3)

DZF

(6)

External

MUTE

(5)

Mute ON

Notes:

(1) The analog output corresponding to digital input has the group delay (GD).

(2) Analog outputs are floating (Hi -Z) at the power-down mode.

(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.

(4) The external clocks (MCKI, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).

(5) Please mute the analog output externally if the click noise (3) influences system application.

The timing example is shown in this figure.

(6) DZF pin is “L” in the power-down mode (PDN = “L”).

Figure 7. Power-down/up sequence example

MS0015-E-01

- 19 -

2000/07

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