SCC68692 데이터 시트보기 (PDF) - Philips Electronics
부품명
상세내역
일치하는 목록
SCC68692 Datasheet PDF : 30 Pages
| |||
Philips Semiconductors
Dual asynchronous receiver/transmitter (DUART)
Product specification
SCC68692
AC CHARACTERISTICS1, 2, 4
SYMBOL FIGURE
PARAMETER
LIMITS
Min
Typ3
Max
UNIT
Reset Timing
tRES
1
RESET pulse width
200
Bus Timing5
tAS
4,5,6
A1–A4 setup time to CSN Low
10
tAH
4,5,6
A1–A4 hold time from CSN Low
100
tRWS
4,5,6
RWN setup time to CSN High
0
tRWH
4,5,6
RWN holdup time to CSN High
0
tCSW8
4,5,6
CSN High pulse width
160
tCSD9
4,5,6
CSN or IACKN High from DTACKN Low
20
tDD
4,5,6
Data valid from CSN or IACKN Low
tDA8
4
RDN Low to data bus active
15
tDF8
4,5,6
Data bus floating from CSN or IACKN High
tDI8
4
RDN High to data bus invalid
20
tDS
4,5,6
Data setup time to CLK High
100
tDH
4,5,6
Data hold time from CSN High
0
tDAL
4,5,6
DTACKN Low from read data valid
0
tDCR
4,5,6
DTACKN Low (read cycle) from CLK High
tDCW
4,5,6
DTACKN Low (write cycle) form CLK High
tDAH
4,5,6
DTACKN High from CSN or IACKN High
IDAT
4,5,6
DTACKN High impedance from CSN or IACKN High
tCSC7
4,5,6
CSN or IACKN setup time to clock High
90
Port Timing5
tPS
7
Port input setup time to CSN Low
0
tPH
7
Port input hold time from CSN High
0
tPD
7
Port output valid from CSN High
Interrupt Timing
tIR10
6
INTRN (or OP3–OP7 when used as interrupts) negated from:
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY interrupt)
Reset command (break interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
ns
ns
ns
ns
ns
ns
ns
175
ns
ns
125
ns
ns
ns
ns
ns
125
ns
125
ns
100
ns
125
ns
ns
ns
ns
400
ns
300
ns
300
ns
300
ns
300
ns
300
ns
300
ns
Clock Timing
tCLK
7
fCLK11
7
tCTC
7
fCTC9
7
tRX
7
fRX9
7
tTX
7
fTX9
7
X1/CLK High or Low time
X1/CLK frequency
CTCLK (IP2) High or Low time
CTCLK (IP2) frequency
RxC High or Low time
RxC frequency (16X)
(1X)
TxC High or Low time
TxC frequency (16X)
(1X)
100
0
3.6864
4
100
100
4
220
100
2
100
1
220
0
2
0
1
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
Transmitter Timing
tTXD
8
TxD output delay from TxC external clock input on IP pin
tTCS
8
Output delay from TxC low at OP pin to TxD data output
350
ns
150
ns
Receiver Timing
tRXS
9
RxD data setup time before RxC high at external clock input on IP pin
240
ns
tRXH
9
RxD data hold time after RxC high at external clock input on IP pin
200
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
1998 Sep 04
7
Share Link: 