SC92031 데이터 시트보기 (PDF) - Silan Microelectronics

부품명

상세내역

일치하는 목록

SC92031

10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER

Silan Microelectronics 

SC92031

(Continued)

Pin No.

Symbol

Description

98, 10, 20, 31 C/BE3-0B PCI bus command and byte enables.

14

DEVSELB Device Select, target is driving to indicate the address is decoded.

11

FRAMEB Begin and duration of bus access, driven by master device.

PCI bus granted. This signal indicates that the PCI bus request of SC92031

85

GNTB

has been accepted.

PCI bus request, the SC92031 will assert this signal low to request the

86

REQB

ownership of the bus from the central arbiter.

Initialization Device Select. This pin allows the SC92031 to identify when

99

IDSEL

configuration read/write transactions are intended for it.

PCI interrupt request. It is asserted low when an interrupt condition occurs,

81

INTAB

as defined by the Interrupt Status, Interrupt Mask and Interrupt Enable

registers.

12

IRDYB

Master device is ready to data transaction.

13

TRDYB

Slave device is ready to data transaction.

Parity, this signal indicates even parity across AD31-0 and C/BE3-0

19

PAR

including the PAR pin. As a master, PAR is asserted during address and

write data phases. As a target, PAR is asserted during read data phases.

16

PERRB

Data parity error is detected, driven by the agent receiving data.

18

SERRB

Address parity error.

15

STOPB

The current target is requesting the master to stop the current transaction.

Power Management/Isolation Interface

Power Management Event, Open drain, active low. Used by the SC92031 to

87

PMEB

request a change in its current power management state and/or to indicate

that a power management event has occurred.

LAN WAKE-UP signal, This signal is used to inform the motherboard to

execute the wake-up process. The motherboard must support Wake-On-

71

LWAKE

LAN (WOL). There are 4 choices of output, including active high, active low,

positive pulse, and negative pulse, that may be asserted from the LWAKE

pin.

EEPROM Interface

This pin is used to notify the SC92031 of the existence of Aux. power during

initial power-on or a PCI reset. This pin should be pulled high to the Aux.

49

AUX

power via a resistor to detect the Aux. power. Doing so, will enable wakeup

support from ACPI D3 cold or APM power-down. If this pin is not pulled

high, the SC92031 assumes that no Aux. power exists.

EEPROM Interface

47

EECK

EEPROM chip serial clock

46

EEDI

EEPROM chip serial data in

45

EEDO

EEPROM chip serial data out

48

EECS

EEPROM chip select

(To be continued)

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

Http: www.silan.com.cn

REV:1.0 2004.08.03

Page 5 of 38

Share Link: