SC84502 데이터 시트보기 (PDF) - Silan Microelectronics

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SC84502

PS/2 MOUSE CONTROLLER

Silan Microelectronics 

Silan

Semiconductors

SC84502

Byte

1

2

3

Bit

Description

0

Left button status; 1 = pressed

1

Right button status; 1 = pressed

2

Middle button status; 1 = pressed

3

Reserve

4

X data sign; 1 = negative

5

Y data sign; 1 = negative

6

X data overflow; 1 = overflow

7

Y data overflow; 1 = overflow

0-7

X data(D0 ~ D7)

0-7

Y data(D0 ~ D7)

3.PS/2 MOUSE DATA TRANSMISSION

i) SC84502 generates the clocking signal when sending data to and receiving data from the system.

ii) The system requests SC84502 receive system data output by forcing the DATA line to an inactive level and

allowing CLK line to go to an active level.

iii) Data transmission frame:

Bit

1

2~9

10

11

Function

Start bit(always 0)

Data bits(D0 ~D7)

Parity bit(odd parity)

Stop bit (always 1)

iv) Data Output (data from SC84502 to system)

If CLK is low (inhibit status), data is no transmission.

If CLK is high and DATA is low(request-to-send), data is updated. Data is received from the system and no

transmission are started by SC84502 until CLK and DATA both high. If CLK and DATA are both high, the

transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge of CLK.

During transmission, SC84502 check for line contention by checking for an inactive level on CLK at

intervals not to exceed 100µ sec. Contention occurs when the system lowers CLK to inhibit SC84502

output after SC84502 has started a transmission. If this occurs before the rising edge of the contention

does not occur by the tenth clock, the transmission is complete.

Following a transmission, the system inhibits SC84502 by holding CLK low until it can service the input or

until the system receives a request to send a response from SC84502.

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

Rev: 1.0 2000.12.31

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