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SC1406G

Power Supply Controller for Portable Pentium II & III SpeedStep Processors

Semtech Corporation 

SC1406G

POWER MANAGEMENT

Functional Description

SUPPLY

The chip is optimized to operate from a 3.3V + 5% rail but is

also designed to work up to 6V maximum supply voltage.

UNDER VOLTAGE LOCK-OUT CIRCUIT

The under voltage lockout (UVLO) circuit consists of two com-

parators, the low battery and low VCC (low supply voltage)

comparators. The output of the comparator, gated with the

Enable signal, turns on or off the internal bias, enables or

disables the CO output, and initiates or resets the soft start

timers.

POWER GOOD GENERATOR

If the chip is enabled but not in UVLO condition, and the core

voltage gets within +10% of the VID programmed value, then a

high level Power Good signal is generated on the PWRGD pin to

trigger the CPU power up sequence. If the chip is either disabled

or enabled in UVLO condition, then PWRGD stays low. This

condition is satisfied by the presence of an internal 200kW pull-

down resistor connected from PWRGD to ground.

During soft start, PWRGD stays low independently from the

status of Vcore voltage.

PWRGD is high when all of the following conditions are true:

1 EN is high

2 Soft-start has completed

3 LBIN and VCC are above their under-voltage trip levels.

Current Limit Comparator

The current limit comparator monitors the core converter output

current and turns the high side switch off when the current

exceeds the upper current limit threshold, VHCL and re-enable

only if the load current drops below the lower current limit

threshold, VLCL. The current is sensed by monitoring the

voltage drop across the current sense resistor, RCS, connected in

series with the core converter main inductor (the same resistor

used for IMVP input signal generation). The thresholds have the

following relationships:

VHCL

= 3 • RCLOH

R CLSET

•V REF

VLCL

= 2 • RCLOH

R CLSET

•V REF

VHYSCL

=

R CLOH

R CLSET

•V REF

Core Converter Soft Start Timer

This circuit controls the ramp-up time of the core voltage in

order to reduce the initial inrush current on the core input

voltage (battery) rail. The soft-start circuit consists of an internal

current source, external soft-start timing capacitor, internal

discharge switch across the capacitor, and a comparator

monitoring the capacitor voltage.

BAND GAP REFERENCE

A better than +1% precision band-gap reference acts as the

internal reference voltage standard of the chip, which all critical

biasing voltages and currents are derived from. All references to

VREF in the equations to follow will assume VREF = 1.7V.

CORE CONVERTER CONTROLLER

Precision VID DAC Reference

The 5-bit digital to analog converter (DAC) serves as the pro-

grammable reference source of the core comparator. Program-

ming is accomplished by CMOS logic level VID code applied to

the DAC inputs. The VID code vs. the DAC output is shown in the

Output Voltage Table. The accuracy of the VID DAC is main-

tained on the same level as the band gap reference. There is a

10µA pull-up current on each DAC input when EN is high.

LINEAR REGULATOR CONTROLLERS

1.5V Linear Regulator

This block is a low drop-out (LDO) linear-regulator controller,

which drives an external PNP bipolar transistor as a pass

element. The linear regulator is capable of delivering 500mA

steady-state DC current and can support transient currents of

greater than 1A, depending on pass element and output

capacitor selection.

2.5V Linear Regulator

This block is a low drop-out (LDO) linear regulator controller,

which drives an external PNP bipolar transistor as a pass

element. The LDO linear regulator is capable of delivering

100mA steady-state DC current and can support transient

currents greater than 200mA, depending on pass element and

output capacitor selection.

Core Comparator

This is an ultra-fast hysteretic comparator with a typical propaga-

tion delay of approximately 20ns at a 20mV overdrive.

This chip can be used in a standard hysteretic mode controller

configuration and in an IMVP hysteretic controller scheme.

Linear Regulator Soft-Start

The soft-start circuit of the linear regulators is similar to that of

the core converter, and is used to control the ramp-up time of

the linear regulator output voltages. For maximum flexibility in

controlling the start-up sequence, the soft-start function of the

linear regulators is separated from that of the core converter.

Detailed instructions for the IMVP solution are found in the

PowerStep™ solution design procedure section of this

datasheet.

ã 2000 Semtech Corp.

9

www.semtech.com

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