ADP3820ART-4.1Z-RL7 데이터 시트보기 (PDF) - Analog Devices
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ADP3820ART-4.1Z-RL7 Datasheet PDF : 8 Pages
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ADP3820
PCB Layout Issues
For optimum voltage regulation, place the load as close as pos-
sible to the device’s VOUT and GND pins. It is recommended to
use dedicated PCB traces to connect the MOSFET’s drain to
the positive terminal and GND to the negative terminal of the
load to avoid voltage drops along the high current carrying PCB
traces.
If PCB layout is used as heatsink, adding many vias around the
power FET helps conduct more heat from the FET to the back-
plane of the PCB, thus reducing the maximum FET junction
temperature.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead Plastic Surface Mount Package
RT-6 (SOT-23-6)
0.122 (3.10)
0.106 (2.70)
0.071 (1.80)
6
5
4
0.118 (3.00)
0.059 (1.50)
0.098 (2.50)
1
2
3
PIN 1
0.037 (0.95) BSC
0.075 (1.90)
BSC
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
0.006 (0.15)
0.000 (0.00)
10؇
0.020 (0.50) SEATING 0.009 (0.23) 0؇
0.010 (0.25) PLANE
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
8-Lead Narrow Body Package
SO-8
0.1968 (5.00)
0.1890 (4.80)
8
0.1574 (4.00)
0.1497 (3.80) 1
5
0.2440 (6.20)
4 0.2284 (5.80)
PIN 1
0.0500 (1.27)
BSC
0.0196 (0.50)
0.0099 (0.25) ؋ 45؇
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
8؇
0.0192 (0.49)
0.0098 (0.25) 0؇
0.0138 (0.35)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
–8–
REV. A
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