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SAA7128AH

Digital video encoder

Philips Electronics 

Philips Semiconductors

Digital video encoder

Product specification

SAA7128AH; SAA7129AH

7.3.2 TELETEXT INSERTION AND ENCODING

Pin TTX receives a WST or NABTS teletext bitstream

sampled at the LLC clock. Two protocols are provided:

• At each rising edge of output signal (TTXRQ) a single

teletext bit has to be provided after a programmable

delay at input pin TTX

• The signal TTXRQ performs only a single LOW-to-HIGH

transition and remains at HIGH level for 360, 296 or 288

teletext bits, depending on the chosen standard.

Phase variant interpolation is achieved on this bitstream in

the internal teletext encoder, providing sufficient small

phase jitter on the output text lines.

TTXRQ provides a fully programmable request signal to

the teletext source, indicating the insertion period of

bitstream at lines which are selectable independently for

both fields. The internal insertion window for text is set to

360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)

teletext bits including clock run-in bits. The protocol and

timing are illustrated in Fig.23.

7.3.3 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING

Five bytes of VPS information can be loaded via the

I2C-bus and will be encoded in the appropriate format into

line 16.

7.3.4 CLOSED CAPTION ENCODER

Using this circuit, data in accordance with the specification

of closed caption or extended data service, delivered by

the control interface, can be encoded (line 21). Two

dedicated pairs of bytes (two bytes per field), each pair

preceded by run-in clocks and framing code, are possible.

The actual line number where data is to be encoded in, can

be modified in a certain range.

The data clock frequency is in accordance with the

definition for NTSC-M standard 32 times horizontal line

frequency.

Data LOW at the output of the DACs corresponds to 0 IRE,

data HIGH at the output of the DACs corresponds to

approximately 50 IRE.

It is also possible to encode closed caption data for 50 Hz

field frequencies at 32 times horizontal line frequency.

7.3.5 ANTI-TAPING (SAA7128AH ONLY)

For more information contact your nearest Philips

Semiconductors sales office.

7.4 RGB processor

This block contains a dematrix in order to produce red,

green and blue signals to be fed to a SCART plug.

Before Y, CB and CR signals are de-matrixed, individual

gain adjustment for Y and colour difference signals and

2 times oversampling for luminance and 4 times

oversampling for colour difference signals is performed.

The transfer curves of luminance and colour difference

components of RGB are illustrated in Figs 12 and 13.

7.5 SECAM processor

SECAM specific pre-processing is achieved by a

pre-emphasis of colour difference signals (for gain and

phase see Figs 14 and 15).

A baseband frequency modulator with a reference

frequency shifted from 4.286 MHz to DC carries out

SECAM modulation in accordance with appropriate

standard or optionally wide clipping limits.

After the HF pre-emphasis, also applied on a DC reference

carrier (anti-Cloche filter; see Figs 16 and 17), line-by-line

sequential carriers with black reference of 4.25 MHz (Db)

and 4.40625 MHz (Dr) are generated using specified

values for FSC programming bytes.

Alternating phase reset in accordance with SECAM

standard is carried out automatically. During vertical

blanking, the so-called “bottle pulses” are not provided.

7.6 Output interface/DACs

In the output interface, encoded Y and C signals are

converted from digital-to-analog in a 10-bit resolution.

Y and C signals are also combined to a 10-bit CVBS

signal.

The CVBS output occurs with the same processing delay

(equal to 82 LLC clock periods, measured from MP input

to the analog outputs) as the Y, C and RGB outputs.

Absolute amplitude at the input of the DAC for CVBS is

reduced by 15⁄16 with respect to Y and C DACs to make

maximum use of conversion ranges.

Red, green and blue signals are also converted from

digital-to-analog, each providing a 9-bit resolution.

Outputs of the DACs can be set together via software

control to minimum output voltage (approximately 0.2 V

DC) for either purpose. Alternatively, the buffers can be

switched into 3-state output condition; this allows for a

‘wired AND’ configuration with other 3-state outputs and

can also be used as a power-save mode.

2003 Dec 09

11

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