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SAA4952WP

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Objective specification

SAA4952WP

FUNCTIONAL DESCRIPTION

The SAA4952WP is a memory controller intended to be

used for scan conversion in TV receivers. This conversion

is performed from 50 to 100 Hz or from 60 to 120 Hz.

Besides the doubling of the field frequency a progressive

scan conversion can be activated (50 Hz/1250 lines or

60 Hz/1050 lines). For low cost PALplus receivers a

simple 50 Hz/1fH mode can be performed. The device

supports up to three separate PLL circuits. The acquisition

PLL can operate with frequencies of 12, 13.5, 16 or

18 MHz. In a three-clock system the deflection PLL

operates with 27 MHz (see Fig.11). An additional display

PLL generates 32 or 36 MHz. If a two-clock system is

chosen the deflection PLL can operate with all possible

display frequencies (27, 32 and 36 MHz) and the extra

PLL can be omitted (see Fig.12). In a system using the

deflection processor TDA9151, three PLLs are necessary

because the 27 MHz clock is needed for the deflection.

If other deflection processors are used (e.g. TDA9152) two

PLLs are sufficient. The 50 Hz/1fH mode operates with a

single clock.

Frequency doubling is possible for input data rates of

12, 13.5, 16 and 18 MHz. Displaying a 4 : 3 picture on a

16 : 9 screen is possible by using the clock configuration

12/32 MHz and 13.5/36 MHz. A 14 : 9 picture can be

displayed on a 16 : 9 screen by the frequency

combinations 16/36 MHz or 12/32 MHz. The VCO and

loop filter are peripheral parts of each PLL, the clock

divider and generation of the reference pulse for the phase

detector are internally provided.

The device generates all write, read and clock pulses to

control a field memory in the desired mode. The required

signals are programmable via an 8-bit parallel

microcontroller port.

Figure 1 shows the block diagram of the SAA4952WP.

The clock signal LLA from the VCO is input at pin 13, a

horizontal reference pulse HRA for the phase discriminator

is output at pin 11. By setting the clock divider to different

values the PLL can be forced to operate with different

clock frequencies. The acquisition part can also be

configured to operate with an external clock frequency

from a digital source. Pin 11 is used as an input pin.

The horizontal reference pulse BLNA is supplied externally

to reset the horizontal counters. This mode is intended to

be used together with, for example, a digital colour

decoder which provides the clock and reference pulses.

The signals HWE1, CLV and HVACQS are generated in

the horizontal acquisition processing part. The vertical

processing block supplies the signals RSTW1 as well as a

vertical enable signal (VWE1) for the combined write

enable signal with a horizontal and vertical part (WE1).

The START and STOP position of the pulses are

programmable, whereas the increment equals 2 (4) clock

cycles in the horizontal part and 1 line in the vertical part.

For HWE1 an additional 2-bit fine delay is available.

Display related control signals are derived from the display

clock. The functions are similar to the acquisition part.

The clock frequency can be switched to 27, 32 or 36 MHz.

In the event of a three-clock system using the TDA9151

the 27 MHz clock frequency is generated by an additional

deflection PLL. In the horizontal part the pulses HWE2,

HR2, HD and BLND are programmable in increments of

2 (4) clock cycles, each one adjustable by an additional

2-bit fine delay. The vertical processing block generates

VDFL and enable signals for the horizontal part (VWE2,

VRE1, VRE2 and VD).

The 16 kHz PLL reference pulse HRDFL is generated from

the display clock frequencies (27, 32 or 36 MHz) and the

32 kHz deflection pulse HDFL. In the three-clock system

the deflection pulses are derived from an extra 27 MHz

clock, independent of the chosen mode of the scan

converter module.

The field length of two successive fields is measured in the

vertical acquisition part. The sampling of VACQ is

performed internally via the signal HVACQS, a pulse

which occurs every 32 µs. The position of this pulse is

programmable via the microcontroller interface to ensure

correct sampling of VACQ.

The measured length of the fields can be read by the

microcontroller. Depending on these values the

microcontroller selects an appropriate setting to achieve

an optimized display performance.

The 100 Hz vertical synchronizing signal VDFL is

generated in accordance with the measured length of the

incoming fields. The position towards the video data of this

pulse can also be selected by the microcontroller.

Furthermore two field identification signals for 50 Hz and

for 100 Hz are generated internally to mark the

corresponding display fields for the microcontroller.

The SAA4952WP supports two different Multi

Picture-In-Picture (MPIP) modes. In addition to the

features of the SAA4951WP the new controller is able to

generate a 3 × 3 MPIP without an external PIP module.

The PIP is obtained in a simple way by storing each third

pixel and line of the source into the memory. The display

is able to run free and is not synchronized to the PIP

source in this mode. One of the nine MPIPs can show a

live picture while the others are frozen.

1997 Jun 10

6

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