MC74HC280 데이터 시트보기 (PDF) - Motorola => Freescale
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MC74HC280 Datasheet PDF : 6 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9-Bit Odd/Even Parity
Generator/Checker
High–Performance Silicon–Gate CMOS
The MC74HC280 is identical in pinout to the LS280. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This circuit consists of 9 data–bit inputs (A through I) and 2 outputs (Even
Parity and Odd Parity) to allow both odd and even parity applications. Words
greater than 9–bits can be accommodated by cascading other HC280
devices.
This device can be used in systems utilizing the LS180 parity generator/
checker. Although the HC280 does not have expander inputs, the
corresponding function is provided by an input at pin 4 and the absence of
any connection at pin 3. This permits the HC280 to be substituted for the
LS180 to produce a similar function, even if the HC280s are mixed with
existing LS180s. NOTE: Pullup resistors must be used on the LS180 outputs
to interface with the HC280.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 226 FETs or 56.5 Equivalent Gates
LOGIC DIAGRAM
A8
B9
C 10
9–BIT D 11
DATA–
WORD
INPUTS
E 12
F 13
G1
H2
I4
5 EVEN PARITY PARITY
6 ODD PARITY OUTPUTS
VCC = PIN 14
GND = PIN 7
NO CONNECTION = PIN 3
MC74HC280
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
ORDERING INFORMATION
MC74HCXXXN
MC74HCXXXD
Plastic
SOIC
PIN ASSIGNMENT
G1
H2
NC 3
I4
EVEN PARITY 5
ODD PARITY 6
GND 7
14 VCC
13 F
12 E
11 D
10 C
9B
8A
NC = NO CONNECTION
FUNCTION TABLE
Outputs
Number of Inputs A through Even Odd
I That are High
Parity Parity
0, 2, 4, 6, 8
H
L
1, 3, 5, 7, 9
L
H
10/95
© Motorola, Inc. 1995
1
REV 6
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