RT9595 데이터 시트보기 (PDF) - Richtek Technology

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RT9595

MOSFET Integrated Smart Photoflash Capacitor Charger with IGBT Driver

Richtek Technology 

RT9595

False Triggering Prevention

The RT9595 includes a mechanism to prevent false

triggering of DRVOUT while the device is still in charging

mode.

With this mechanism, the DRVIN pin is only allowed to

trigger DRVOUT when the CHARGE pin is low.

DRVIN

BUF

DRVOUT

CHARGE

Figure 4. Trigger Logic

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = (TJ(MAX) − TA) / θJA

Where TJ(MAX) is the maximum operation junction

temperature , TA is the ambient temperature and the θJA is

the junction to ambient thermal resistance.

For recommended operating conditions specification, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance θJA is layout dependent. For

WDFN-10L 3x3 packages, the thermal resistance θJA is

60°C/W on the standard JEDEC 51-7 four layers thermal

test board. The maximum power dissipation at TA = 25°C

can be calculated by following formula :

PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for

WDFN-10L 3x3 packages

The maximum power dissipation depends on operating

ambient temperature for fixed TJ(MAX) and thermal

resistance θJA. For WDFN-10L 3x3 package, the Figure 5

of derating curves allows the designer to see the effect of

rising ambient temperature on the maximum power

allowed.

1.8

Four Layers PCB

1.6

1.4

1.2

WDFN-10L 3x3

1.0

0.8

0.6

0.4

0.2

0.0

0

25

50

75

100

125

Ambient Temperature (°C)

Figure 5. Derating Curve of Maximum Power Dissipation

Layout Consideration

For best performance, the following guidelines should be

strictly followed.

` Both of primary and secondary power paths should be

as short as possible.

` Place the RCS as close to chip as possible. The GND

side of RCS should be directly connected to ground plane

to avoid noise coupling.

` Keep FB node area small and far away from nodes with

voltage switching to reduce parasitic capacitance

coupling effect.

` The PGND should be connected to VBAT ground plane

to reduce switching noise.

PGND

VOUT

Bottom

GND 1

DRVOUT 2

VDD 3

DRVIN 4

CHARGE 5

10 SW

PGND

9 NC

VBAT

8 CS

7 FB RCS

GND

11 6 STAT

GND

Figure 6. Recommended Layout Guideline

Copyright ©2012 Richtek Technology Corporation. All rights reserved.

www.richtek.com

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is a registered trademark of Richtek Technology Corporation.

DS9595-04 March 2012

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