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RT9645

5 Channels ACPI Regulator

Richtek Technology 

Preliminary

RT9645

100

FZ1 FZ2 FP1 FP2

80

60

Open Loop Error

AMP Gain

40

20

20LOG

(R1/R2)

0

-20

Modulator

Gain

-40

20LOG

(VIN/ΔVOSC)

Compensation

Gain

Closed Loop Gain

FLC

FESR

-60

10

100

1K

10K 100K 1M

10M

Frequency (Hz)

Figure 8

Feedback Loop Design Procedure

Use these guidelines for locating the poles and zeros of

the compensation network :

1. Pick Gain (R2/R1) for desired 0dB crossing frequency

(FC).

2. Place 1st zero FZ1 below modulator double pole FLC

(~75% FLC).

3. Place 2nd zero FZ2 at modulator double pole FLC.

4. Place 1st pole FP1 at the ESR zero FZ_ESR

5. Place 2nd pole FP2 at half the switching frequency.

6. Check gain against error amplifier's open-loop gain.

7. Pick RFB for desired output voltage.

8. Estimate phase margin and repeat if necessary.

Component Selection

Components should be appropriately selected to ensure

stable operation, fast transient response, high efficiency,

minimum BOM cost and maximum reliability.

Output Inductor Selection

The selection of output inductor is based on the

considerations of efficiency, output power and operating

frequency. For a synchronous buck converter, the ripple

current of inductor (%IL) can be calculated as follows :

ΔIL

= (VIN

− VOUT ) ×

VOUT

VIN × IOSC × L

(7)

Generally, an inductor that limits the ripple current between

20% and 50% of output current is appropriate. Make sure

that the output inductor could handle the maximum output

current and would not saturate over the operation

temperature range.

Output Capacitor Selection

The output capacitors determine the output ripple voltage

(%VOUT) and the initial voltage drop after a high slew rate

load transient. The selection of output capacitor depends

on the output ripple requirement. The output ripple voltage

is described as Equation (8).

ΔVOUT

=

ΔIL

× ESR +

1×

8 IO2 SC

VOUT

× L × COUT

(1− D)

(8)

For electrolytic capacitor application, typically 90 to 95%

of the output voltage ripple is contributed by the ESR of

output capacitors. Paralleling lower ESR ceramic capacitor

with the bulk capacitors could dramatically reduce the

equivalent ESR and consequently the ripple voltage.

Input Capacitor Selection

Use mixed types of input bypass capacitors to control

the input voltage ripple and switching voltage spike across

the MOSFETs. The buck converter draws pulsewise

current from the input capacitor during the on time of upper

MOSFET. The RMS value of ripple current flowing through

the input capacitor is described as :

IIN(RMS) = IOUT × D × (1− D)

The input bulk capacitor must be cable of handling this

ripple current. Sometime, for higher efficiency the low ESR

capacitor is necessarily. Appropriate high frequency

ceramic capacitors physically near the MOSFETs

effectively reduce the switching voltage spikes.

MOSFET Selection of PWM Buck Converter

The selection of MOSFETs is based upon the

considerations of RDS(ON), gate driving requirements, and

thermal management requirements. The power loss of

upper MOSFET consists of conduction loss and switching

loss and is expressed as :

PUPPER = PCOND _ UPPER + PSW _ UPPER

=

IO2 UT

× RDS(ON)

×D

+

1

2

IOUT

×

VIN

×

(TRISE

+

TFALL

) × IOSC

DS9645-00 August 2007

www.richtek.com

11

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