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RT9244

Multi-Phase PWM Controller for CPU Core Power Supply

Richtek Technology 

RT9244

The sensing circuit gets IX = IL × RS by local feedback.

RSP

RSP = RSN to cancel the voltage drop caused by GM amplifier

input bias current. IX is sampled and held just before low

side MOSFET turns off (See Figure 2). Therefore,

IX (S/H) = IL (S/H) × R S , IL (S/H) = IL (AVG) − V O × T OFF ,

R SP

L2

T OFF

=

⎡ V IN − V O ⎤

⎢⎣ V IN ⎥⎦

×

5uS

for

fosc

= 200kHz

I X (S/H)

⎡

⎢

= ⎢IL(AVG)

−

VO

−

⎡ V IN − V O ⎤

⎢⎣ V IN ⎥⎦

×

5uS

⎤

⎥

⎥×

RS

⎢

2L

⎥ R SP

⎢⎣

⎥⎦

Falling Slope = Vo/L

IL

Inductor Current

IL(S/H)

IL(AVG)

PWM Signal & High Side MOSFET Gate Signal

Low Side MOSFET Gate Signal

Figure 2. Inductor Current and PWM Signal

DAC Offset Voltage & Droop Tuning

The DAC offset voltage is set by compensation network

& VOSS pin external resistors by

⎜⎛ 1V ⎟⎞ × R f1

⎝ R VOSS ⎠ 4

.

The S/H current signals from power channels are injected

∑ to ADJ pin to create droop voltage. VADJ = RADJ× 2IX

The DAC output voltage decreases by VADJ to form the

VCORE load droop (see Figure 3).

COMP +

EA

-

Current

Source

IVOSS = 1V

RVOSS

>

1

4

IVOSS

VOSS

RVOSS

VDAC

VADJ

∑

FB

ADJ

RF1

RADJ

2IX1

2IX2

2IX3

2IX4

VCORE

Figure 3. DAC Offset Voltage & Droop Tune Circuit

Protection and SS Function

For OVP, the RT9244 detects the VCORE by VDIF pin voltage

of the differential amplifier output. Eliminate the delay due

to compensation network (compared to sensing FB voltage)

for fast and accurate detection. The trip point of OVP is

140% of normal output level. The PWM outputs are pulled

low to turn on the low side MOSFET and turn off the high

side MOSFET of the synchronous rectifier at OVP. The

OVP latch can only be reset by VCC or DVD restart power

on reset sequence. The PGOOD detection trip point of

VCORE is 92% lower than the normal level. The PGOOD

open drain output pulls low when VCORE is lower than the

trip point. For VID jumping issue, only power fail conditions

(VCC & DVD are lower than trip point or OVP) reset the

output low.

Soft-start circuit generates a ramp voltage by charging

external capacitor with 13μA current after IC POR acts.

The PWM pulse width and VCORE are clamped by the rising

ramp to reduce the inrush current and protect the power

devices.

Over-current protection trip point is internally set at around

100μA for each channel. OCP is triggered if one channel

S/H current signal IX > ⎜⎛ 0.6V ⎟⎞ × 1.5. Controller forces

⎝ 9K ⎠

PWM output latched at high impedance to turn off both

high and low side MOSFETs in the power stage and initial

the hiccup mode protection. The SS pin voltage is pulled

low with a 13μA current after it is less than 90% VCC. The

converter restarts after SS pin voltage < 0.2V. Three times

of OCP disable the converter and only release the latch by

POR acts (see Figure 4).

CCOoUuNnTt ==11 CCOoUuNntT==22 CCOoUuNntT==33

S.S

VCORE

0V

Overload

Applied

ILOAD

0A

T0,T1

T2

T3,T4

TIME

Figure 4.

www.richtek.com

10

DS9244-06 March 2007

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