AD8401 데이터 시트보기 (PDF) - Analog Devices
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AD8401 Datasheet PDF : 12 Pages
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AD8401
Pin#
1
2
3
4
5
6
7–12, 14, 15
13
16
17
18
19
20
21
22
23
27–24
28
REV. 0
PIN CONFIGURATION
DICE CHARACTERISTICS
VDD 1
AGDAC 2
VOUT 3
NC 4
A1 5
RS 6
DB7 7
DB6 8
DB5 9
28 A0
27 VINA
26 VINB
25 VINC
24 VIND
23 AGADC
AD8401AR
Top View
(Not to Scale)
22 CLK
21 INT
20 BUSY
DB4 10
19 ST
DB3 11
18 RD
DB2 12
17 CS
DGND 13
DB1 14
16 WR
15 DB0
NC = NO CONNECT
32
1
28
27
26
25
24
23
5
6
7
8
9
10
PIN DESCRIPTIONS
22
21
20
19
18
11 12 13 14 15 16 17
Die Size 91 X 121 mil = 11,011 sq mil
Name
Description
VDD
AGDAC
VOUT
NC
A1
RESET (RS)
DB7 to DB0
DGND
WR
CS
RD
ST
BUSY
INT
CLK
AGADC
VINA, B, C, D
A0
Positive Supply. Nominal value +5 volts. This pad requires 2 bonds for die assembly.
The substrate is common with VDD.
Analog Ground for the DAC. There is a separate analog ground for the ADC.
Voltage Output from the DAC.
No Connect.
Address Input that controls multiplexer. See Table I for address decode.
Active Low Digital Input that clears the DAC register to zero, setting the DAC to mini-
mum scale. It also asynchronously clears the INT line of the ADC.
Digital I/O Lines. DB7 (7) is the Most Significant Bit (MSB), for both the ADC and
the DAC, and DB0 (15) is the Least Significant Bit (LSB).
Digital Ground.
Rising Edge Triggered Write Input. Used to load data into the DAC register.
Chip Select. Active Low Input
Active Low Read Input. When this input is active, ADC data can be read from the
part. RD going low starts the ADC conversion.
Falling Edge Triggered Start Input. Used for applications requiring precise sample tim-
ing. The falling edge of ST starts the conversion and sets the BUSY low. The ST is not
gated by CS.
ADC Active Low, Status Output. When the ADC is performing a conversion, the
BUSY output is low.
Active Low Output. The Interrupt output notifies the system that the ADC has com-
pleted its conversion. INT goes high on the rising edge of CS or RD. It will also be
forced high when RESET is asserted.
External Clock Input Pin. Accepts a TTL or 5 V CMOS input logic levels.
Analog ADC Ground
Four Analog Inputs
Address input that controls multiplexer. See Table I for address decode.
–5–
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