RT8057 데이터 시트보기 (PDF) - Richtek Technology
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RT8057 Datasheet PDF : 11 Pages
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RT8057
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8057, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For
WDFN-6SL 2x2 packages, the thermal resistance, θJA, is
165°C/W on a standard JEDEC 51-3 single-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (165°C/W) = 0.606W for
WDFN-6SL 2x2 package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. For the RT8057 package, the derating
curve in Figure 2 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0
Single-Layer PCB
25
50
75
100
125
Ambient Temperature (°C)
Figure 2. Derating Curve for the RT8057 Package
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the RT8057.
} Connect the terminal of the input capacitor(s), CIN, as
close as possible to the VIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
} LX node experiences high frequency voltage swing and
should be kept within a small area. Keep all sensitive
small-signal nodes away from the LX node to prevent
stray capacitive noise pick up.
} Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to any DC net
(VIN, VOUT, GND, or any other DC rail in the system).
} Connect the FB pin directly to the feedback resistors.
The resistive voltage divider must be connected between
VOUT and GND.
LX should be connected to inductor by
wide and short trace. Keep sensitive
components away from this trace.
COUT
VOUT
L1
LX 1
VOUT
NC 2
C1 FB 3
R1
R2
6 GND
CIN
5 VIN
7 4 EN
Input capacitor must
be placed as close to
the IC as possible.
Figure 3. PCB Layout Guide
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10
DS8057-03 November 2011
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