CY7C4231-10JC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C4231-10JC

64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

Switching Waveforms

Write Cycle Timing

WCLK

D0 –D8

WEN1

tCLKH

tCLK

tCLKL

tDS

tENS

WEN2

(if applicable)

FF

RCLK

tWFF

tSKEW1 [11]

REN1,REN2

Read Cycle Timing

RCLK

REN1,REN2

tENS

EF

Q0 –Q8

OE

tOLZ

WCLK

WEN1

tCLKH

tCKL

tCLKL

tENH

tREF

tA

NO OPERATION

tOE

[12]

tSKEW1

CY7C4421/4201/4211/4221

CY7C4231/4241/4251

tDH

tENH

tWFF

NO OPERATION

NO OPERATION

42X1–6

tREF

VALID DATA

tOHZ

WEN2

42X1–7

Notes:

11. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the

rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.

12. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the

rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK rising edge.

6

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