NJU6677
(2) Instruction
The NJU6677 distinguishes the signal on the data bus by combination of A0, RD and WR. The decode of the
instruction and execution performs depending on the internal timing only neither the external clock. In case of
serial interface, the data input as MSB first serially.
The Table. 4 shows the instruction codes of the NJU6677.
Table 4. Instruction Code
(*:Don't Care)
In s truc tio n
Code
W-
A0 RD R D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
D e s c rip ti o n
(1 ) D i s p la y O N /O F F
0 1 0 1 0 1 0 1 1 1 0 L C D D i s p la y O N /O F F
1 0 :O F F 1 :O N
D i s p la y S ta rt L ine S e t 0 1 0 0 1 0 1
(2 ) H i g h O rd e r 4 b its
H igh O rd e r
A d d ress
D e te rm i n e the D i s p la y L i n e o f
R A M to the C O M 0 .
(S e t the H igher order 4bits)
D i s p la y S ta rt L ine S e t 0 1 0 0 1 1 0
Lower Order 4bits
Lower Order
A d d ress
D e te rm i n e the D i s p la y L i n e o f
R A M to the C O M 0 .
(S e t the L o w e r o r d e r 4 b i ts )
(3 ) P a g e A d d re s s S e t
4 b its
0 1 0 1 1 0 0 P a g e A d d re s s S e t th e 4 b it p a g e o f D D R A M
to the P a g e A d d re s s R e g iste r
(4 ) C o lum n A d d re s s S e t
H i g h O rd e r 4 b its
0 10 00 0 1
H igh O rd e r S e t th e H i g h e r o rd e r 4 bits
C o lum n A d d . C o lum n A d d re s s to the R e g .
C o lum n A d d re s s S e t
Lower Order 4bits
0 10 00 0 0
L o w e r O r d e r S e t th e L o w e r order 4 bits
C o lum n A d d . C o lum n A d d re s s to the R e g .
(5 ) S ta tus R e a d
00 1
S ta tus
0 0 0 0 R e a d o ut the inte rna l S ta tus
(6 ) W rite D i s p la y D a ta
1 10
W rite D a ta
W rite the d a ta into the D i s p la y
D a ta R A M
(7 ) R e a d D i s p la y D a ta
10 1
R e a d D a ta
R e a d the d a ta fro m the D i s p la y
D a ta R A M
( 8 ) N o r m a l o r In v e r s e o f
O N /O F F S e t
0 1 0 1 0 1 0 0 1 1 0 In v e r s e the O N a n d O F F
1 D i s p la y
0 :N o rm a l 1 :Inve r s e
(9 ) W h o le D i s p la y O N
/N o rm a l D i s p la y
0 1 0 1 0 1 0 0 1 0 0 W h o le D i s p la y Turns O N
1 0 :N o rm a l 1 :W h o le D i s p . O N
(1 0 ) S u b i n s truc tio n ta b le
mode
0 1 0 0 1 1 1 0 0 0 0 S e t th e S u b i n s truc ti o n t a b le .
(11 ) P a rtia l D i s p la y
1 s t B lo c k , S e t
S ta rt d i s p la y unit
0 10 00 0 0
S ta rt d i s p la y S e t th e S ta rt d i s p la y unit o f 1 s t
unit
B lo c k .
1 s t B lo c k ,
0 10 00 0 1
S e t The num b e r o f
d i s p la y units
num b e r of
d i s p la y units
S e t th e n u m b e r o f d i s p la y units
o f 1 s t B lo c k .
2 n d B lo c k , S e t
S ta rt d i s p la y unit
0 10 00 10
S ta rt d i s p la y S e t th e S ta rt d i s p la y unit o f 2 n d
unit
B lo c k .
2 n d B lo c k ,
0 10 00 1 1
S e t The num b e r o f
d i s p la y units
num b e r of
d i s p la y units
S e t th e n u m b e r o f d i s p la y units
o f 2 n d B lo c k .
P a rtia l d i s p la y o n
0 1 0 0 1 0 0 0 0 0 0 It c o m e s o ff th e m o d e to s e t
a n d a d i s p la y is e xe c u te d .
( 1 2 ) n - li n e In v e r s e D r i v e
Set
R e g iste r S e t
0 1 0 0 1 0 1 * * hig h e r S e t the num b e r o f inve rse d rive
Higher order 2 bits
o rd e r line .
R e g iste r S e t
0 10 0 1 10
L o w e r o rd e r 4 bits
L o w e r o rd e r
S e t the num b e r o f inve rse d rive
line .
n - li n e In v e r s e D r i v e 0 1 0 0 1 1 1 0 0 0 0 T h e e xe c u t i o n o f th e li n e i n v e r s e
S e t is e xe c u te d .
d rive .
(1 3 ) E V R R e g i s te r S e t
E V R R e g i s te r S e t 0 1 0 1 0 0 0
Higher order 4 bits
E V R D a ta
Higher order
S e t th e V 5 o u tp u t le v e l to the
E V R re g i s te r. (H i g h e r o r d e r 4
b its )
E V R R e g i s te r S e t 0 1 0 1 0 0 1
L o w e r o rd e r 4 bits
E V R D a ta
L o w e r o rd e r
S e t th e V 5 o u tp u t le v e l to the
E V R re g i s te r. (L o w e r o r d e r 4
b its )
E V R R e g i s te r S e t 0 1 0 1 0 1 0 0 0 0 0 The e xe c utio n o f th e E V R .
is e xe c ute d .
(1 4 ) E n d o f s u b i n s truc tio n 0 1 0 0 1 1 1 0 0 0 1 It e n d s the s e tting o f s u b
ta b le m o d e
ins truc tio n ta b le .