RC4200 데이터 시트보기 (PDF) - Fairchild Semiconductor

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RC4200

Analog Multiplier

Fairchild Semiconductor 

RC4200

PRODUCT SPECIFICATION

Functional Description

The RC4200 multiplier is designed to multiply two input

currents (I1 and I2) and to divide by a third input current (I4).

The output is also in the form of a current (I3). A simplified

circuit diagram is shown in the Block Diagram. The nominal

relationship between the three inputs and the output is:

I3

=

I---1--I---2-

I4

(1)

The three input currents must be positive and restricted to a

range of 1 µA to 1 mA. These currents go into the multiplier

chip at op amp summing junctions which are nominally at

zero volts. Therefore, an input voltage can be easily

converted to an input current by a series resistor. Any

number of currents may be summed at the inputs. Depending

on the application, the output current can be converted to a

voltage by an external op amp or used directly. This capa-

bilty of combining input currents and voltages in various

combinations provides great versatility in application.

Inside the multiplier chip, the three op amps make the

collector currents of transistors Q1, Q2 and Q4 equal to their

respective input currents (I1, I2, and I4). These op amps are

designed with current source outputs and are phase-compen-

sated for optimum frequency response as a multiplier. Power

drain of the op amps was minimized to prevent the introduc-

tion of undesired thermal gradients on the chip. The three op

amps operate on a single supply voltage (nominally -15V)

and total quiescent current drain is less than 4 mA. These

special op amps provide significantly improved performance

in comparison to 741-type op amps.

The actual multiplication is done within the log-antilog

configuration of the Q1-Q4 transistor array. These four

transistors, with associated proprietary circuitry, were

specially designed to precisely implement the relationship.

VBEN

=

k----T-- In -I--C---N--

Q ISN

(2)

Previous multiplier designs have suffered from an additional

undesired linear term in the above equation; the collector

current times the emitter resistance. The ICrE term intro-

duces a parabolic nonlinearity even with matched transistors.

Fairchild Semiconductor has developed a unique and propri-

etary means of inherently compensating for this undesired

ICrE term. Furthermore, this Fairchild Semiconductor devel-

oped circuit technique compensates linearity error over tem-

perature changes. The nonlinearity versus temperature is

significantly improved over earlier designs.

From equation (2) and by assuming equal transistor junction

temperatures, summing base-to-emitter voltage drops around

the transistor array yields:

K-----T-- In--I--1--- = In--I--2--- – In--I--3--- –In--I--4--- = 0 (3)

q IS1

IS2 IS3 IS4

This equation reduces to:

I---1--I---2- = -I--S---1---I--S---2- (4)

I3I4 IS3IS4

The rate of reverse saturation current IS1IS2/IS3IS4, depends

on the transistor matching. In a monolithic multiplier this

matching is easily achieved and the rate is very close to

unity, typically 1.0±1%. The final result is the desired

relationship:

I3

=

I---1--I---2-

I4

(5)

The inherent linearity and gain stability combined with low

cost and versatility makes this new circuit ideal for a wide

range of nonlinear functions.

Pin Assignments

I2 1

VOS2 2

–VS 3

I3 (Output) 4

8 I1

7 VOS1

6 GND

5 I4

65-4200-07

2

REV. 1.2.1 6/14/01

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