R5F212C7SDFP 데이터 시트보기 (PDF) - Renesas Electronics

부품명

상세내역

일치하는 목록

R5F212C7SDFP

RENESAS MCU

Renesas Electronics 

R8C/2C Group, R8C/2D Group

2. Central Processing Unit (CPU)

2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.

Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0

when an interrupt request is acknowledged.

2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.

The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software

interrupt numbers 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has higher priority than IPL, the interrupt is enabled.

2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.

Rev.1.00 Feb 09, 2007 Page 16 of 55

REJ03B0183-0100

Share Link: