QL4016 데이터 시트보기 (PDF) - QuickLogic Corporation
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QL4016 Datasheet PDF : 35 Pages
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Military QuickRAM Family Data Sheet Rev. C
Table 8: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns) Fanout
1
2
3
4
5
tSRA
tHRA
tSRE
tHRE
tRCRD
RA Setup Time to RCLK
RA Hold Time to RCLK
RE Setup Time to RCLK
RE Hold Time to RCLK
RCLK to RDa
1.0
1.0
1.0
1.0
1.0
0.0
0.0
0.0
0.0
0.0
1.0
1.0
1.0
1.0
1.0
0.0
0.0
0.0
0.0
0.0
4.0
4.3
4.6
4.9
6.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage and temperature settings as specified in Table 4.
Table 9: RAM Cell Asynchronous Read Timing
Symbol
RPDRD
Parameter
RA to RDa
Propagation Delays (ns) Fanout
1
2
3
4
5
3.0
3.3
3.6
3.9
5.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Table 4.
Table 10: Input-Only/Clock Cells
Symbol
Parameter
Propagation Delays (ns) Fanouta
1 2 3 4 8 12 24
tIN
High Drive Input Delay
1.5 1.6 1.8 1.9 2.4 2.9 4.4
tINI
High Drive Input, Inverting Delay
1.6 1.7 1.9 2.0 2.5 3.0 4.5
tISU
Input Register Set-Up Time
3.1 3.1 3.1 3.1 3.1 3.1 3.1
tIH
Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
tICLK
Input Register Clock To Q
0.7 0.8 1.0 1.1 1.6 2.1 3.6
tIRST
Input Register Reset Delay
0.6 0.7 0.9 1.0 1.5 2.0 3.5
tIESU
Input Register Clock Enable Setup Time
2.3 2.3 2.3 2.3 2.3 2.3 2.3
tIEH
Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25°C. Multiply by the appropriate
Delay Factor, K, for speed grade, voltage and temperature settings as specified in Table 4.
© 2007 QuickLogic Corporation
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