PT6324 데이터 시트보기 (PDF) - Princeton Technology

부품명

상세내역

일치하는 목록

PT6324

VFD Driver/Controller IC

Princeton Technology 

PT6324

DISPLAY TIMING

The Key Scanning and display timing diagram is given below. One cycle of key scanning consists of 2 frames. The data

of the 16 x 2 matrix is stored in the RAM.

Internal Operating Frequency (fosc) = 224/T

Note: T is the width of Segment only

SERIAL COMMUNICATION FORMAT

The following diagram shows the PT6324 serial communication format. The DIN/DOUT Pin is an Schmitt trigger circuit

and N-channel, open-drain output pin, therefore, it is highly recommended that an external pull-up resistor (1KΩ to 10KΩ)

must be connected to DIN/DOUT when using key scan function.

where: twait (waiting time) ≥ 1µs

It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the

command and the falling of the first clock that has read the data is greater or equal to 1µs.

V1.5

10

June 2010

Share Link: