SL4034BD 데이터 시트보기 (PDF) - System Logic Semiconductor

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SL4034BD

8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register High-Voltage Silicon-Gate CMOS

System Logic Semiconductor 

SL4034B

TRUTH TABLE FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER

OPERATION

“A”

Enable P/S A/B A/S

Operation*

L

L L X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled

L

L H X Serial Mode, Synch. Serial Data Input, “B” Parallel Data Output

L

H L L Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs

Disabled

L

H L H Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs

Disabled

L

H H L Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs,

Synch. Data Recirculation

L

H H H Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs,

Asynch. Data Recirculation

H

L L X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output

H

L H X Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output

H

H L L Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output

H

H L H Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output

H

H H L Parallel Mode; “A” Synch. Parallel Data Input, “B” Parallel Data Output

H

H H H Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output

* Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low”

in the parallel mode. During transfer from parallel to serial operation A/S should remain low in oder to prevent DS

transfer into Flip Flops.

X = Don’t Care

PARALLEL OPERATION

A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with

the positive transition of the clock provided the A/S input is low. If the A/S input is high the transfer is

independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the

A data lines are inputs (and B data lines are outputs); a low A/B signal reverses the direction of data flow.

The AE input is an additional feature which allows many registers to feed data to a common bus. The A

DATA lines are enabled only when this signal is high.

Data storage through recirculation of data in each register stage is accomplished by making the A/B signal

high and the AE signal low.

SERIAL OPERATION

A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of

the clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial

operation is not allowed).

The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is

low and the AE signal is high).

SLS

System Logic

Semiconductor

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