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PNX8526

Programmable source decoder with integrated peripherals

Philips Electronics 

Philips Semiconductors

PNX8526

Programmable Source Decoder with Integrated Peripherals

Table 3: Peripheral Controller Interface (PCI)…continued

# indicates multiplexed signal, see Section 6.2.1 for more details.

Symbol

Pin

Type Description

Alternate

Function

C/BE[1]

AE8 I/O

Multiplexed Command or Byte Enable 1

C/BE[0]

AD10 I/O

Multiplexed Command or Byte Enable 0

CLK

AA1 I

PCI Bus Clock

DEVSEL

AF7 I/O

Device Select is asserted when a target address is decoded and remains

asserted to indicate that a target device is selected.

FRAME

AF6 I/O

Frame is asserted to indicate start of bus transaction and remains

asserted until final data phase begins.

GNT

Y3

I/O

Arbitration Grant is asserted to indicate access to the bus has been

granted. This pin is an input when an external arbiter is used and an

output when using the internal arbiter.

GNT_A

Y4

I/O

Auxiliary Arbitration Grant_A is asserted to indicate bus access has been

#

granted to an external PCI master. Used where internal arbiter is

configured.

GNT_B

AA4 I/O

Auxiliary Arbitration Grant_B is asserted to indicate bus access has been

#

granted to an external PCI master. Used where internal arbiter is

configured.

IDSEL

AF3 I/O

Initialization Device Select provides chip select during configuration read

and write transactions.

INTA

V4

I/O

Interrupt A is asserted to request an interrupt. This pin may be configured

as an input if the internal PIC is used, or as an output if the external

interrupt controller is used. Polarity in active low.

IRDY

AE6 I/O

Initiator Ready is asserted during writes to indicate valid data on

AD[31:0]. Also asserted during reads to indicate the target is prepared to

accept data. Wait states are inserted until IRDY and TRDY are both

asserted.

PAR

AF8 I/O

Parity supports even parity across the PCI Address/Data Bus AD[31:0])

and Command/ Byte Enable Bus (C/BE[3:0]). The Bus Master drives PAR

for address and write data phases. The Target drives PAR for the read

data phases.

PERR

AD7 I/O

Parity Error indicates data parity errors during all PCI transactions except

Special Cycle.

REQ

Y2

I/O

Arbitration Request on PCI Bus. Request is an output when using an

external arbiter and an input when using an internal arbiter.

REQ_A

AA2 I/O

Auxiliary Arbitration REQ_A on PCI Bus. Used in modes where internal

#

arbiter is configured.

REQ_B

AA3 I/O

Auxiliary Arbitration REQ_B on PCI Bus. Used in modes where internal

#

arbiter is configured.

RESET_IN

W3

I

PCI Bus Global Reset

SERR

AC7 I/O

System Error

STOP

AE7 I/O

Stop is asserted to indicate a request from the target for the master to

stop the current transmission.

TRDY

AD6 I/O

Target Ready is asserted during reads to indicate valid data on AD[31:0].

It is asserted during writes to indicate the target is prepared to accept

data. Wait states are inserted until IRDY and TRDY are both asserted.

9397 750 11715

Preliminary data

Rev. 01 – 6 October 2003

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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