HEF4068BN 데이터 시트보기 (PDF) - Philips Electronics
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HEF4068BN Datasheet PDF : 3 Pages
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Philips Semiconductors
8-input NAND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL TYP.
MAX.
Propagation delays
In → O
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10
tPHL
15
5
10
tPLH
15
5
10
tTHL
15
5
10
tTLH
15
95
195
ns
40
85
ns
30
65
ns
80
165
ns
35
70
ns
30
60
ns
60
120
ns
30
60
ns
20
40
ns
60
120
ns
30
60
ns
20
40
ns
Product specification
HEF4068B
gates
TYPICAL EXTRAPOLATION
FORMULA
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
53 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
700 fi + ∑(foCL) × VDD2
where
10
2900 fi + ∑(foCL) × VDD2
fi = input freq. (MHz)
15
7200 fi + ∑(foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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