74HC/HCT354 데이터 시트보기 (PDF) - Philips Electronics

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74HC/HCT354

8-input multiplexer/register with transparent latches; 3-state

Philips Electronics 

Philips Semiconductors

8-input multiplexer/register with

transparent latches; 3-state

Product specification

74HC/HCT354

FEATURES

• Transparent data latches

• Transparent address latch

• Easily expanding

• Complementary outputs

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT354 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT354 data selectors/multiplexers contain full

on-chip binary decoding, to select one-of-eight data

sources. The data select address is stored in transparent

latches that are enabled by a LOW on the latch enable

input (LE).

The transparent 8-bit data latches are enabled when the

active LOW data enable input (E) is LOW. When the output

enable input OE1 = HIGH, OE2 = HIGH or OE3 = LOW,

the outputs go to the high impedance OFF-state.

Operation of these output enable inputs does not affect the

state of the latches.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL PARAMETER

CONDITIONS

tPHL/ tPLH

CI

CPD

propagation delay

Dn, E to Y, Y

Sn, LE to Y, Y

input capacitance

power dissipation capacitance per latch

CL = 15 pF; VCC = 5 V

notes 1 and 2

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

TYPICAL

UNIT

HC HCT

20 22 ns

24 27 ns

3.5 3.5 pF

68 71 pF

December 1990

2

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