PLL103-06 데이터 시트보기 (PDF) - PhaseLink Corporation
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PLL103-06 Datasheet PDF : 7 Pages
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Preliminary PLL103-06
DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS
3. Electrical Specifications (Continued)
PARAMETERS
Supply Current
(DDR-only mode)
Supply Current
(SDRAM mode)
Supply Current
Output Crossing
Voltage
Output Voltage Swing
Duty Cycle
Max. Operating
Frequency
Rising Edge Rate
Falling Edge Rate
DDR Rising Edge Rate
DDR Falling Edge Rate
Clock Skew(pin to pin)
Stabilization Time
Note: TBM: To be measured
SYMBOL
IDD
IDD
IDDS
VOC
VOUT
DT
TOR
TOF
TOR
TOF
TSKEW
TST
CONDITIONS
Unloaded outputs, 133MHz
Unloaded outputs, 133MHz
PD = 0
Measured @ 1.5V
Measured @ 0.4V ~ 2.4V
Measured @ 2.4V ~ 0.4V
Measured between 20% to 80% of
output
Measured between 20% to 80% of
output
All outputs equally loaded
MIN.
(VDD/2)
-0.1
0.7
45
66
1.0
1.0
0.25
0.25
TYP.
MAX.
TBM
VDD/2
50
1.5
1.5
0.6
TBM
TBM
(VDD/2)+
0.1
VDD-0.4
55
170
2.0
2.0
1.0
0.6
1.0
100
0.1
UNITS
mA
mA
mA
V
V
%
MHz
V/ns
V/ns
V/ns
V/ns
ps
ms
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 12/20/00 Page 6
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