PLL102-108XC 데이터 시트보기 (PDF) - PhaseLink Corporation
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PLL102-108XC Datasheet PDF : 10 Pages
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PLL102-108
Programmable DDR Zero Delay Clock Driver
4. BYTE 3: Outputs Register (1=Enable, 0=Disable)
Bit
Name
Default
Description
Bit 7
-
1
Reserved
Bit 6
Bit 5
Bit 4
Skew
FBOUT
Bit <2>
Bit <1>
Bit <0>
0
These three bits will adjust timing of FBOUTT signal either positive
1
or negative delay up to +800ps or –600ps with ±200ps per step.
1
(see Table 1)
Bit 3
Bit <3>
0
Bit 2
Bit 1
Delay
CLKINT
Bit <2>
Bit <1>
0
These four bits will program the propagation delay from CLK_INT
to the input of PLL within the range between 0ps and 2.5ns with
0
170ps step size. (see Table 2)
Bit 0
Bit <0>
0
TABLE 2: CLK_INT Delay Programming Summary:
Bit<3:0>
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
CLK_INT to CLK Delay
+2,550 ps
+2,380 ps
+2,210 ps
+2,040 ps
+1,870 ps
+1,700 ps
+1,530 ps
+1,360 ps
+1,190 ps
+1,020 ps
+850 ps
+680 ps
+510 ps
+340 ps
+170 ps
Default
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 03/29/02 Page 5
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