ICS300MT-XX 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS300MT-XX

QTClock™ Quick Turn Clock Synthesizer

Integrated Circuit Systems 

ICS300/ICS301/ICS302

QTClock™ Quick Turn Clock Synthesizer

Electrical Specifications

Parameter

Conditions

Minimum Typical

ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)

Supply Voltage, VDD

Referenced to GND

Inputs

Referenced to GND

-0.5

Clock Output

Referenced to GND

-0.5

Ambient Operating Temperature

0

Soldering Temperature

Max of 10 seconds

Storage temperature

-65

DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)

Operating Voltage, VDD

3

Input High Voltage, VIH, ICLK only

ICLK (Pin 1)

(VDD/2)+1 VDD/2

Input Low Voltage, VIL, ICLK only

ICLK (Pin 1)

VDD/2

Input High Voltage, VIH

PDTS

2

Input Low Voltage, VIL

PDTS

Output High Voltage, VOH

IOH=-4mA

VDD-0.4

Output High Voltage, VOH

IOH=-25mA

2.4

Output Low Voltage, VOL

IOL=25mA

IDD Operating Supply Current, 20 MHz crystal No Load, 100MHz

20

Short Circuit Current

CLK output

±70

On-Chip Pull-up Resistor, PDTS

Pin 7

270

Input Capacitance, PDTS

Pin 7

4

AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)

Input Frequency, crystal input, ICS300 and 301

5

Input Frequency, clock input, ICS300 and 301

2

Input Frequency, clock input, ICS302

50

Output Frequency, ICS300

VDD = 4.5 to 5.5V

6

Output Frequency, ICS300

VDD = 3.0 to 3.6V

6

Output Frequency, ICS301 and ICS302

VDD = 4.5 to 5.5V

6

Output Frequency, ICS301 and ICS302

VDD = 3.0 to 3.6V

6

Output Clock Rise Time

0.8 to 2.0V

1

Output Clock Fall Time

2.0 to 0.8V

1

Output Clock Duty Cycle (Note 1)

at programmed level

45

49 to 51

Absolute Clock Period Jitter

Deviation from mean

±120

One Sigma Clock Period Jitter

50

Power-up time, PDTS goes high until Refer. out Reference on REF clk

3

Power-up time, PDTS goes high until CLK out

8

Maximum

7

VDD+0.5

VDD+0.5

70

260

150

5.5

(VDD/2)-1

0.4

0.4

27

50

125

160

100

200

200

55

10

20

Units

V

V

V

°C

°C

°C

V

V

V

V

V

V

V

V

mA

mA

kΩ

pF

MHz

MHz

MHz

MHz

MHz

MHz

MHz

ns

ns

%

ps

ps

ms

ms

Note 1: These are typical values. The actual minimum and maximum duty cycle limits are shown on the

ICS300/301/302 QTClock Order Form for each programmed version.

MDS 300QT E

3

Revision 111000

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel• www.icst.com

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