SL74HC595 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL74HC595
System Logic Semiconductor
SL74HC595 Datasheet PDF : 10 Pages
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SL74HC595
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
V
Tsu
Minimum Setup Time,Serial Data
2.0
Input A to Shift Clock (Figure 5)
4.5
6.0
Tsu
Minimum Setup Time, Shift Clock to
2.0
Latch Clock (Figure 6)
4.5
6.0
th
Minimum Hold Time, Shift Clock to
2.0
Serial Data Input A (Figure 5)
4.5
6.0
Trec Minimum Recovery Time, Reset
2.0
Inactive to Shift Clock (Figure 2)
4.5
6.0
Tw
Minimum Pulse Width, Reset (Figure
2.0
2)
4.5
6.0
Tw
Minimum Pulse Width, Shift Clock
2.0
(Figure 1)
4.5
6.0
Tw
Minimum Pulse Width, Latch Clock
2.0
(Figure 6)
4.5
6.0
tr, tf Maximum Input Rise and Fall Times
2.0
(Figure 1)
4.5
6.0
Guaranteed Limit
25 °C to
-55°C
≤85°C ≤125°C Unit
50
65
75
ns
10
13
15
9
11
13
75
95
110
ns
15
19
22
13
16
19
5
5
5
ns
5
5
5
5
5
5
50
65
75
ns
10
13
15
9
11
13
60
75
90
ns
12
15
18
10
13
15
50
65
75
ns
10
13
15
9
11
13
50
65
75
ns
10
13
15
9
11
13
1000
1000
1000
ns
500
500
500
400
400
400
SLS
System Logic
Semiconductor
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