SL74HC4094N 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL74HC4094N
System Logic Semiconductor
SL74HC4094N Datasheet PDF : 7 Pages
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SL74HC4094
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 5)
tPLH, tPHL Maximum Propagation Delay, Clock to SQH
(Figures 1 and 5)
tPLH, tPHL Maximum Propagation Delay, Clock to QA-QH
(Figures 2 and 5)
tPLZ, tPHZ Maximum Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
tPZL, tPZH Maximu m Propagation Delay ,Output Enable to
QA-QH (Figures 3 and 6)
CIN
Maximum Input Capacitance
COUT Maximum Three-State Output Capacitance
(Output in High-Impedance State), QA-QH
VCC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
2.0
6
5
4
MHz
4.5 30
25
20
6.0 35
28
23
2.0 150
190
225
ns
4.5 30
38
45
6.0 26
33
38
2.0 195
245
295
ns
4.5 40
50
60
6.0 33
42
50
2.0 125
155
190
ns
4.5 25
31
38
6.0 21
26
32
2.0 175
220
265
ns
4.5 35
44
53
6.0 30
37
45
-
10
10
10
pF
-
15
15
15
pF
Power Dissipation Capacitance (Per Package)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
300
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
V
tsu
Minimum Setup Time, Serial Data
2.0
Input A to Clock (Figure 4)
4.5
6.0
th
Minimum Hold Time, Clock to Data
2.0
Input A (Figure 4)
4.5
6.0
tw
Minimum Pulse Width, Strobe (Figure 2.0
1)
4.5
6.0
tr, tf Maximum Input Rise and Fall Times
2.0
(Figure 1)
4.5
6.0
Guaranteed Limit
25 °C to
-55°C
≤85°C ≤125°C Unit
50
65
75
ns
10
13
15
9.0
11
13
3
3
3
ns
3
3
3
3
3
3
80
100
120
ns
16
20
24
14
17
20
1000
1000
1000
ns
500
500
500
400
400
400
SLS
System Logic
Semiconductor
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