SL74HC165 데이터 시트보기 (PDF) - System Logic Semiconductor
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SL74HC165
System Logic Semiconductor
SL74HC165 Datasheet PDF : 7 Pages
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SL74HC165
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
High-Performance Silicon-Gate CMOS
The SL74HC165 is identical in pinout to the LS/ALS165. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device is an 8-bit shift register with complementary outputs
from the last stage. Data may be loaded into the register either in
parallel or in serial form. When the Serial Shift/ Parallel Load input is
low, the data is loaded asynchronously in parallel. When the Serial
Shift/Parallel Load input is high, the data is loaded serially on the rising
edge of either Clock or Clock Inhibit (see the Function Table).
The 2-input NOR clock may be used either by combining two
independent clock sources or by designating one of the clock inputs to
act as a clock inhibit.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
ORDERING INFORMATION
SL74HC165N Plastic
SL74HC165D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
PIN 16=VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Internal Stages Output
Serial Shift/
Clock Clock SA A-H QA QB-QG
QH
Parallel Load
Inhibit
L
H
X X a...h a
b-g
h
H
L
LX
L
QAn-QFn
QGn
H
L HX
H
QAn-QFn
QGn
H
L
H
L
LX
HX
L
QAn-QFn
QGn
H
QAn-QFn
QGn
H
X
H XX
no change
H
H
X XX
H
L
L XX
X = Don’t Care
QAn-QFn = Data shifted from the preceding stage
no change
Operation
Asynchronous Parallel Load
Serial Shift via Clock
Serial Shift via Clock
Inhibit
Inhibited Clock
No Clock
SLS
System Logic
Semiconductor
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