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MC54/74HC597A
SWITCHING WAVEFORMS
tw
tr
tf
90%
VCC
1/fmax
tw
VCC
LATCH CLOCK
50%
SHIFT CLOCK
50%
10%
GND
GND
tPLH
tPHL
QH
90%
50%
10%
tTLH
tTHL
Figure 1. (Serial Shift/Parallel Load = L)
RESET
tPHL
QH
tw
50%
50%
SHIFT CLOCK
VCC
GND
trec
Figure 3.
tPLH
tPHL
QH
50%
Figure 2. (Serial Shift/Parallel Load = H)
SERIAL SHIFT/
PARALLEL LOAD
QH
tw
50%
tPLH
50%
VCC
50%
GND
tPHL
Figure 4.
VALID
VALID
PARALLEL DATA
VCC
SERIAL DATA
VCC
A/H
50%
GND
INPUT SA
50%
GND
tsu
th
tsu
th
VCC
VCC
LATCH CLOCK
50%
SHIFT CLOCK
50%
GND
GND
Figure 5.
Figure 6.
SERIAL SHIFT/
VCC
PARALLEL LOAD
50%
GND
tsu
SHIFT CLOCK
50%
VCC
GND
Figure 7.
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 8. Test Circuit
High–Speed CMOS Logic Data
7
DL129 — Rev 6
MOTOROLA