PE9701 데이터 시트보기 (PDF) - Peregrine Semiconductor Corp.

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PE9701

3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications

Peregrine Semiconductor Corp. 

PE9701

Product Specification

Table 1. Pin Descriptions (continued)

Pin No. Pin Name Interface Mode Type

31

VDD-fp

ALL

(Note 1)

32

Dout

Serial, Parallel

Output

33

VDD

ALL

(Note 1)

34

Cext

ALL

Output

35

VDD

ALL

36

CP

ALL

37

NC

ALL

(Note 1)

Output

Description

VDD for fp

Data Out. The MSEL signal and the raw prescaler output are available on Dout

through enhancement register programming.

Same as pin 1.

Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.

Connecting Cext to an external capacitor will low pass filter the input to the inverting

amplifier used for driving LD.

Same as pin 1.

Charge pump current is sourced for “up” when fc leads fp and sinked for “down”

when fc lags fp.

No connection.

38

VDD-fc

ALL

39

fc

ALL

40

GND

ALL

(Note 1)

Output

VDD for fc

Monitor pin for reference divider output. Switching activity can be disabled through

enhancement register programming or by floating or grounding VDD pin 38.

Ground.

41

GND

ALL

Ground.

42

fr

ALL

Input

Reference frequency input.

43

LD

44

Enh

ALL

Serial, Parallel

Output,

OD

Input

Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is

high impedance, otherwise LD is a logic low (“0”).

Enhancement mode. When asserted low (“0”), enhancement register bits are

functional.

Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.

VDD pins 31 and 38 are used to enable test modes and should be left floating.

Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.

©2003-2006 Peregrine Semiconductor Corp. All rights reserved.

Page 4 of 13

Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions

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