3340-00 데이터 시트보기 (PDF) - Peregrine Semiconductor Corp.

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3340-00

3.0 GHz Integer-N PLL for Low Phase Noise Applications

Peregrine Semiconductor Corp. 

PE3340

Advance Information

Functional Description

The PE3340 consists of a prescaler, counters, a

phase detector and control logic. The dual modulus

prescaler divides the VCO frequency by either 10 or

11, depending on the value of the modulus select.

Counters “R” and “M” divide the reference and

prescaler output, respectively, by integer values

stored in a 20-bit register. An additional counter

(“A”) is used in the modulus select logic.

Figure 3. Functional Block Diagram

The phase-frequency detector generates up and

down frequency control signals. Data is written into

the internal registers via the three wire serial bus.

There are also various operational and test modes

and a lock detect output.

fr

R Counter

(6-bit)

fc

Sdata

Control

Pins

Control

Logic

R(5:0)

M(8:0)

A(3:0)

Phase

Detector

Modulus

Select

Fin

Fin

10/11

Prescaler

M Counter

(9-bit)

fp

PD_U

PD_D

2 kΩ

LD

Cext

Copyright © Peregrine Semiconductor Corp. 2004

Page 6 of 12

File No. 70/0040~02A| UTSi ® CMOS RFIC SOLUTIONS

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