PDSP16488AC0AC 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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PDSP16488AC0AC Datasheet PDF : 33 Pages
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PDSP16488A
333 WINDOW
LINE N21 C4 C5 C6
LINE N C8 C9 C10
LINE N11 C0 C1 C2
IP7:0
ODD
FIELD
FIELD
DELAY
VIDEO
L7:0
LINE N12
1024
N11
1024 N21 434
OR
1024
834
N ARRAY
1024
Output is shifted
by 1 line in
every field
535 WINDOW
LINE N22 C48 C49 C50 C51 C52
LINE N21 C8 C9 C10 C11 C12
LINE N C40 C41 C42 C43 C44
LINE N11 C0 C1 C2 C3 C4
LINE N12 C32 C33 C34 C35 C36
IP7:0
ODD
FIELD
FIELD
DELAY
VIDEO
L7:0
LINE N12
DELAY
BYPASSED
REG B BIT 7 SET
512
N11
512 N21
512
512
838
512
ARRAY
N12
512 N
512 N22
512
Output is shifted
by 1 line in
every field
838 WINDOW
LINE N23 C24 C25 C26 C27 C28 C29 C30 C31
LINE N22 C56 C57 C58 C59 C60 C61 C62 C63
LINE N21 C16 C17 C18 C19 C20 C21 C22 C23
LINE N C48 C49 C50 C51 C52 C53 C54 C55
LINE N11 C8 C9 C10 C11 C12 C13 C14 C15
LINE N12 C40 C41 C42 C43 C44 C45 C46 C47
LINE N13 C0 C1 C2 C3 C4 C5 C6 C7
LINE N14 C32 C33 C34 C35 C36 C37 C38 C39
IP7:0
ODD
FIELD
FIELD
DELAY
VIDEO
L7:0
LINE N14
DELAY
BYPASSED
REG B BIT 7 SET
512
N13
512 N11
512 N21
512 N23
838
512
ARRAY
N14
512 N12
512 N
512 N22
Output is shifted
by 2 lines in
every field
Fig. 5 Line delay allocations in SINGLE device interlaced systems
8
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