PD488588 데이터 시트보기 (PDF) - Elpida Memory, Inc

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PD488588

288M bits Direct Rambus DRAM

Elpida Memory, Inc 

µPD488588

32. RSL - Transmit Timing

Figure 32-1 is a timing diagram which shows the detailed requirements for the RSL output signals on the Channel.

The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel.

Each signal is driven twice per tCYCLE interval. The beginning and end of the even transmit window is at the 75 %

point of the previous cycle and at the 25 % point of the current cycle. The beginning and end of the odd transmit

window is at the 25 % point and at the 75 % point of the current cycle. These transmit points are measured relative to

the crossing points of the falling CTM clock edge. The size of the actual transmit window is less than the ideal

tCYCLE/2, as indicated by the non-zero valued of tQ,MIN and tQ,MAX. The tQ parameters are measured at the 50 % voltage

point of the output transition.

The tQR and tQF rise- and fall-time parameters are measured at the 20 % and 80 % points of the output transition.

CTM

CTMN

DQA

DQB

Figure 32-1 RSL Timing - Data Signals for Transmit

VX-

0.75•t CYCLE

tQR

VCM

VX+

tQ,MAX

0.75•t CYCLE

0.25•t CYCLE

tQ,MIN tQ,MAX

tQ,MIN

even

odd

t QF

VCIH

80%

50%

20%

VCIL

VQH

80%

50%

20%

VQL

Data Sheet E0039N30 (Ver. 3.0)

61

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