Philips Semiconductors
50–150 MHz 1:9 SDRAM clock driver
Product specification
PCK2509SL
PARAMETER MEASUREMENT INFORMATION
FROM OUTPUT
UNDER TEST
30 pF
500 Ω
LOAD CIRCUIT FOR OUTPUTS
3V
INPUT
50% VCC
tpe
0V
OUTPUT
2V
0.4 V
tr
50% VCC
2V
VOH
0.4 V VOL
tf
VOLTAGE WAVEFORMS & PHASE ERROR TIMES
NOTES:
1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω , tr ≤ 1.2 ns, tf ≤
13.2 Tnhs.e outputs are measured one at a time with one transition per measurement.
Figure 6. Load Circuit and Voltage Waveforms
SW00384
CLKIN
FBIN
FBOUT
tphase error
ANY Y
ANY Y
tSK(0)
ANY Y
tSK(0)
Figure 7. Phase Error and Skew Calculations
SW00385
2000 Dec 01
8