PCK2010DL 데이터 시트보기 (PDF) - Philips Electronics
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PCK2010DL Datasheet PDF : 16 Pages
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Philips Semiconductors
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
168-pin SDR SDRAM DIMM
BACK SIDE
Preliminary specification
PCK2010
FRONT SIDE
AVC
AVC
AVC
PCK2509S or PCK2510S
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00403
FUNCTION TABLE
SEL
133/100
SEL1
SEL0
CPU
CPUDIV2
3V66
PCI
48MHz
REF
IOAPIC
0
0
0
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
0
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
0
100MHz 50MHz
66MHz
33MHz
HI-Z
14.318MHz 16.67MHz
0
1
1
100MHz 50MHz
66MHz
33MHz
48MHz 14.318MHz 16.67MHz
1
0
0
TCLK/2
TCLK/4
TCLK/4
TCLK/8
TCLK/2
TCLK
TCLK/16
1
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
0
133MHz 66MHz
66MHz
33MHz
HI-Z
14.318MHz 16.67MHz
1
1
1
133MHz 66MHz
66MHz
33MHz
48MHz 14.318MHz 16.67MHz
NOTES:
1. Required for board level ‘‘bed-of-nails” testing.
2. Used to support Intel confidential application.
3. 48MHz PLL disabled to reduce component jitter. 48MHz outputs to be held Hi-Z instead of driven to LOW state.
4. ‘‘Normal” mode of operation.
5. TCLK is a test clock over driven on the XTALIN input during test mode. TCLK mode is based on 133MHz CPU select logic.
6. Required for DC output impedance verification.
7. Frequency accuracy of 48MHz must be +167 PPM to match USB default.
8. Range of reference frequency allowed is MIN = 14.316MHz, NOMINAL = 14.31818MHz, MAX = 14.32MHz
NOTES
1
2
3
4, 7, 8
5, 6
2
3
4, 7, 8
CLOCK OUTPUT
USBCLK7
TARGET FREQUENCY (MHz)
48.0
ACTUAL FREQUENCY (MHz)
48.008
PPM
167
1999 Mar 01
5
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