PCK2010 데이터 시트보기 (PDF) - Philips Electronics
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PCK2010 Datasheet PDF : 16 Pages
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Philips Semiconductors
CK98 (100/133MHz) Spread Spectrum System Clock
Generator
Preliminary specification
PCK2010
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
2,3
REF [0–1]
3.3V 14.318 MHz clock output
5
XTAL_IN
14.318 MHz crystal input
6
XTAL_OUT
14.318 MHz crystal output
8
PCICLK_F
3.3V free running PCI clock
9, 11, 12, 14, 15, 17, 18
PCICLK [1–7]
3.3V PCI clock outputs
21, 22, 25, 26
3V66 [0–3]
3.3V fixed 66MHz clock outputs
28
SEL133/100
Select input pin for enabling 133MHz or 100MHz CPU outputs.
H = 133MHz, L = 100MHz
30
48MHz
3.3V fixed 48MHZ clock output
32, 33
SEL [0–1]
Logic select pins. TTL levels.
34
SPREAD
3.3V LVTTL input. Enables spread spectrum mode when held
LOW.
35
PWRDWN
3.3V LVTTL input. Device enters powerdown mode when held
LOW.
36
CPUSTOP
3.3V LVTTL input. Stops all CPU clocks and 3V66 clocks when
held LOW. CPUDIV_2 output remains on all the time.
37
PCISTOP
3.3V LVTTL input. Stops all PCI clocks except PCICLK_F when
held LOW.
41, 42, 45, 46
CPUCLK [0–3]
2.5V CPU output. 133MHz or 100MHz depending on state of input
pin SEL133/100.
49, 50
CPUDIV_2 [0–1]
2.5V output running at 1/2 CPU clock frequency. 66MHz or 50MHz
depending on state of input pin SEL133/100.
53, 54, 55
IOAPIC [0–2]
2.5V clock outputs running divide synchronous with the CPU clock
frequency. Fixed 16.67 MHz limit.
4, 10, 16, 23, 27, 31, 39
1, 7, 13, 19, 20, 24, 29, 38, 40, 44,
48, 52
VDD3V
VSS
3.3V power supply.
Ground
43, 47, 51, 56
VDD25V
2.5V power supply
NOTES:
1. VDD3V, VDD25V and VSS in the above tables reflects a likely internal POWER and GROUND partition to reduce the effects of internal noise
on the performance of the device. In reality, the platform will be configured with the VDD25V pins tied to a 2.5V supply, all remaining VDD pins
tied to a common 3.3V supply and all VSS pins being common.
1999 Mar 01
3
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