PCK2001R 데이터 시트보기 (PDF) - Philips Electronics
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PCK2001R Datasheet PDF : 12 Pages
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Philips Semiconductors
14.318 – 133 MHz I2C 1:6 clock buffer
Product specification
PCK2001R
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
NOTES
LIMITS
Tamb = 0°C to +70°C
MIN
TYP9
MAX
UNIT
TP
TH
TL
TP
TH
TL
TP
TH
TL
TP
TH
TL
TSDRISE
TSDFALL
TPLH
TPHL
DUTY CYCLE
CLK period
CLK HIGH time
CLK LOW time
CLK period
CLK HIGH time
CLK LOW time
CLK period
CLK HIGH time
CLK LOW time
CLK period
CLK HIGH time
CLK LOW time
Rise time
Fall time
Buffer LH propagation delay
Buffer HL propagation delay
Output Duty Cycle
1, 6
29.9
33MHz
2, 6, 8
12.3
3, 6, 8
12.1
1, 6
14.9
66MHz
2, 6, 8
5.6
3, 6, 8
5.3
1,6
9.9
100MHz
2, 6, 8
3.3
3, 6, 8
3.2
1, 6
7.4
133MHz
2, 6, 8
2.6
3, 6, 8
2.2
4, 6, 10
1.5
4, 6, 11
1.5
6, 7
1.0
6, 7
1.0
Measured at 1.5V 5, 6, 7
45
30.0
14.3
14.1
15.0
6.8
6.5
10.01
4.2
4.1
7.5
3.1
2.7
2.0
2.5
2.4
2.6
50
30.2
16.3
ns
16.1
15.2
8.0
ns
7.7
10.2
5.1
ns
5.0
7.7
3.6
ns
3.2
4.0
V/ns
4.0
V/ns
3.5
ns
3.5
ns
55
%
TSKW
Bus CLK skew
1, 6
150
250
ps
TDDSKW
Device to device skew
500
ps
NOTES:
1. Clock period and skew are measured on the rising edge at 1.5V.
2. TH is measured at 2.4V as shown in Figure 2.
3. TL is measured at 0.4V as shown in Figure 2.
4. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4V and VOH = 2.4V (1 mA) JEDEC specification.
5. Duty cycle should be tested with a 50/50% input.
6. Over MIN (20pF) to MAX (30pF) discrete load, process, voltage, and temperature.
7. Input edge rate for these tests must be faster than 1 V/ns.
8. Calculated at minimum edge rate (1.5ns) to guarantee 45/55% duty cycle at 1.5V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
9. All typical values are at VCC = 3.3V and Tamb = 25°C.
10. Typical is measured with MAX (30pF) discrete load.
11. Typical is measured with MIN (20pF) discrete load.
2000 Jul 25
5
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