LD8088-2 데이터 시트보기 (PDF) - Intel

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LD8088-2

8-BIT HMOS MICROPROCESSOR

Intel 

8088

Bus Operation

The 8088 address data bus is broken into three

parts the lower eight address data bits (AD0 –

AD7) the middle eight address bits (A8–A15) and

the upper four address bits (A16–A19) The ad-

dress data bits and the highest four address bits are

time multiplexed This technique provides the most

efficient use of pins on the processor permitting the

use of a standard 40 lead package The middle eight

address bits are not multiplexed i e they remain val-

id throughout each bus cycle In addition the bus

can be demultiplexed at the processor with a single

address latch if a standard non-multiplexed bus is

desired for the system

Each processor bus cycle consists of at least four

CLK cycles These are referred to as T1 T2 T3 and

T4 (See Figure 8) The address is emitted from the

processor during T1 and data transfer occurs on the

bus during T3 and T4 T2 is used primarily for chang-

Figure 8 Basic System Timing

231456 – 8

10

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