PCA9548A(2009) 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCA9548A
(Rev.:2009)

8-channel I2C-bus switch with reset

NXP Semiconductors. 

NXP Semiconductors

PCA9548A

8-channel I2C-bus switch with reset

6. Functional description

Refer to Figure 1 “Block diagram of PCA9548A”.

6.1 Device address

Following a START condition, the bus master must output the address of the slave it is

accessing. The address of the PCA9548A is shown in Figure 5. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

1 1 1 0 A2 A1 A0 R/W

fixed

hardware

selectable

002aab189

Fig 5. Slave address

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9548A, which will be stored in the control register. If multiple bytes are

received by the PCA9548A, it will save the last byte received. This register can be written

and read via the I2C-bus.

channel selection bits

(read/write)

76543210

B7 B6 B5 B4 B3 B2 B1 B0

channel 0

channel 1

channel 2

channel 3

channel 4

channel 5

channel 6

channel 7

002aab204

Fig 6. Control register

PCA9548A_3

Product data sheet

Rev. 03 — 7 July 2009

© NXP B.V. 2009. All rights reserved.

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