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PCA9545

4-channel I2C switch with interrupt logic and reset

Philips Electronics 

Philips Semiconductors

4-channel I2C switch with interrupt logic and reset

Product data

PCA9545

AC CHARACTERISTICS

SYMBOL

PARAMETER

tpd

fSCL

tBUF

tHD;STA

Propagation delay from SDA to SDn or SCL to SCn

SCL clock frequency

Bus free time between a STOP and START condition

Hold time (repeated) START condition

After this period, the first clock pulse is generated

STANDARD-MODE

I2C-BUS

MIN

MAX

—

0.31

0

100

4.7

—

4.0

—

FAST-MODE I2C-BUS

MIN

MAX

—

0.31

0

400

1.3

—

0.6

—

UNIT

ns

kHz

µs

µs

tLOW

tHIGH

tSU;STA

tSU;STO

tHD;DAT

tSU;DAT

tR

tF

Cb

tSP

LOW period of the SCL clock

HIGH period of the SCL clock

Set-up time for a repeated START condition

Set-up time for STOP condition

Data hold time

Data set-up time

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Capacitive load for each bus line

Pulse width of spikes which must be suppressed

by the input filter

4.7

—

1.3

—

µs

4.0

—

0.6

—

µs

4.7

—

0.6

—

µs

4.0

—

0.6

—

µs

02

3.45

02

0.9

µs

250

—

100

—

ns

—

1000

20 + 0.1Cb3

300

ns

—

300

20 + 0.1Cb3

300

µs

—

400

—

400

µs

—

50

—

50

ns

tVD:DATL

tVD:DATH

tVD:ACK

INT

Data valid (HL)

Data valid (LH)

Data valid Acknowledge

—

1

—

1

µs

—

0.6

—

0.6

µs

—

1

—

1

µs

tiv

tir

Lpwr

Hpwr

RESET

INTn to INT active valid time

INTn to INT inactive delay time

LOW level pulse width rejection or INTn inputs

HIGH level pulse width rejection or INTn inputs

—

4

—

4

µs

—

2

—

2

µs

1

—

1

—

µs

0.5

—

0.5

—

µs

tWL(rst) Pulse width low reset

4

—

4

—

ns

trst

Reset time (SDA clear)

500

—

500

—

ns

tREC:STA Recovery to Start

0

—

0

—

ns

NOTES:

1. Pass gate propagation delay is calculated from the 20 Ω typical RON and the 15 pF load capacitance.

2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) in order to bridge

the undefined region of the falling edge of SCL.

3. Cb = total capacitance of one bus line in pF.

SDA

tBUF

tLOW

tR

tF

SCL

P

tHD;STA

S

tHD;DAT

tHIGH

tSU;DAT

tHD;STA

tSU;STA

Sr

2002 Mar 28

Figure 13. Definition of timing on the I2C-bus

11

tSP

tSU;STO

P

SU00645

853-2302 27311

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