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PCA5007H/F1

Pager baseband controller

Philips Electronics 

Philips Semiconductors

Pager baseband controller

Product specification

PCA5007

6 FUNCTIONAL DESCRIPTION

6.1 General

The PCA5007 contains a high-performance CMOS

microcontroller and the required peripheral circuitry to

implement high-speed pagers for the modern paging

protocols. For this purpose, features such as FSK

demodulator, protocol timer, real-time clock and DC/DC

converter have been integrated on-chip.

The microcontroller embedded within the PCA5007

implements the standard 80C51 architecture and supports

the complete instruction set of the 80C51 with all

addressing modes.

The PCA5007 contains 20 kbytes of OTP program

memory; 1-kbyte of static read/write data memory,

27 I/O lines, two 16-bit timer/event counters, a

fifteen-source two priority-level, nested interrupt structure

and on-chip oscillator and timing circuit.

The PCA5007 devices have several software selectable

modes of reduced activity for power reduction; Idle for the

CPU and standby or off for the DC/DC converter. The Idle

mode freezes the CPU while allowing the RAM, timers,

serial I/O and interrupt system to continue functioning.

The standby mode for the DC/DC converter allows a high

efficiency of the latter at low currents and the off mode

reduces the supply voltage to the battery level. In the off

mode the RAM contents are preserved, the real-time clock

and protocol timer are operating, but all other chip

functions are inoperative.

Two serial interfaces are provided on-chip; a UART serial

interface and an I2C-bus serial interface. The I2C-bus

serial interface has byte oriented master functions allowing

communication with a whole family of I2C-bus compatible

slave devices.

6.2 CPU timing

The internal CPU timing of the PCA5007 is completely

different to other implementations of this core. The CPU is

realized in asynchronous handshaking technology, which

results in extremely low power consumption and low EMC

noise generation.

6.2.1 BASICS

The implementation of the CPU of the PCA5007 as a block

in handshake technology has become possible through

the TANGRAM tool set, developed in the Philips Natlab in

Eindhoven.

TANGRAM is a high level programming language which

allows the description of parallel and sequential processes

that can be compiled into logic on silicon. The CPU has the

following features:

• No clock is needed. Every function within the CPU is self

timed and always runs at the maximum speed that a

given silicon die under the current operating conditions

(supply voltage and temperature) allows.

• The CPU fetches opcodes with maximum speed until a

special mode (e.g. Idle) is entered that stops this

sequence.

• Only bytes that are required are fetched from the

program memory. The dummy read cycles which exist in

the standard 80C51 have been omitted to save power.

• To further speed up the execution of a program, the next

sequential byte is always fetched from the code memory

during the execution of the current command. In the

event of jumps the prefetched byte is discarded.

• Since no clocks are required, the operating power

consumption is essentially lower compared to

conventional architectures and Idle power consumption

is reduced to nearly zero (leakage only).

• Clocks are only required as timing references for

timers/counters and for generating the timing to the

off-chip world.

6.2.2

EXECUTION OF PROGRAMS FROM INTERNAL CODE

MEMORY

When code is executed in internal access mode (EA = 1),

the opcodes are fetched from the on-chip OTP. The OTP

is a self timed block which delivers data at maximum

speed. This is the preferred operating mode of the

PCA5007.

6.2.3

EXECUTION OF PROGRAMS FROM EXTERNAL CODE

MEMORY

When code is executed in external access mode (EA = 0),

the opcodes are fetched from an off-chip memory using

the standard signals ALE, PSEN and P0, P2 for

multiplexed data and address information. In this mode the

identical hardware configurations as for a standard 80C51

system can be used, even if the timing for ALE and PSEN

is slightly different because it is generated from an internal

oscillator.

1998 Oct 07

9

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