HYS64V16220GU 데이터 시트보기 (PDF) - Siemens AG

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HYS64V16220GU

3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module, 3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module

Siemens AG 

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

AC Characteristics (cont’d)3, 4

TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns

Parameter

Symbol

Limit Values

Unit

-8

-8B

PC100-222 PC100-323

-10

PC66

min. max. min. max. min. max.

Note

Refresh Cycle

Refresh Period

(4096 cycles)

Self Refresh Exit Time

tREF

tSREX

Read Cycle

Data Out Hold Time

tOH

Data Out to Low Impedance tLZ

Data Out to High Impedance tHZ

DQM Data Out Disable

tDQZ

Latency

–

64 –

64 –

64 ms 8

10 –

10 –

10 –

ns

9

3

–

3

–

3

–

ns

4

0

–

0

–

0

–

ns

3

8

3

10 3

10 ns

10

–

2

–

2

–

2

CLK

Write Cycle

Data input to Precharge

tDPL

(write recovery)

2

–

2

–

2

–

CLK

Data In to Active/Refresh tDAL

5

–

5

–

5

–

CLK

DQM Write Mask Latency tDQW

0

–

0

–

0

–

CLK

Semiconductor Group

10

1998-08-01

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