MS81V06160-15TA 데이터 시트보기 (PDF) - Oki Electric Industry

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MS81V06160-15TA

(401,408-word × 16-bit) FIFO memory

Oki Electric Industry 

Semiconductor

MS81V06160

Serial Write Clock: SWCK

The SWCK latches the input data on chip when WE is high, and also increments the internal write address pointer.

Data-in setup time tDS, and hold time tDH are referenced to the rising edge of SWCK.

Serial Read Clock: SRCK

Data is shifted out of the data registers. It is triggered by the rising edge of SRCK when RE is high during a read

operation. The SRCK input increments the internal read address pointer when RE is high.

The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same

polarity as data in. The output becomes valid after the access time interval tAC that begins with the rising edge of

SRCK. *There are no output valid time restriction on MS8106160.

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